ELECTRONIC INDUSTRIES
Year:2017 | Volume:8 | Issue:3 |Papers Count:15

These days, many researchers work on RFID EPC-C1 G2 authentication protocols designing with the use of 16-bit PRNGs. However, thanks to short input/output length of such PRNG functions that makes it feasible to convert it, most of such protocols are vulnerable against full secret disclosure attacks. Recently, Moradi et al. in [1] analyzed an EPC-C1 G2 authentication protocol named 𝑆 𝑆 𝑆 𝑆 𝑆 𝑆 + and presented a revised version of the 𝑆 𝑆 𝑆 𝑆 𝑆 𝑆 + protocol. In this paper, we show that unfortunately the revised version of 𝑆 𝑆 𝑅 𝑅 𝑅 𝑅 +protocol, same as its predecessor i. e. 𝑆 𝑆 𝑆 𝑆 𝑆 𝑆 + protocol, is still vulnerable against full secret disclosure attack. In the presented attack, adversary discloses all secrets of the protocol only by eavesdropping one run of the protocol, impersonating the reader in one run of the protocol and doing only 3 × 216 off-line PRNG function evaluations.

In this paper a novel single layer dual band reflectarray antenna with orthogonal polarization in X and Ku bands for satellite communication is proposed. The planar reflectarray prototype is fabricated and the results are compared with those of simulations and discussed. The unit cell consists of dual split rectangle loops for lower band frequency at 11. 5 GHz and gradually decreasing dipoles for upper band at center frequency of 14 GHz. Both of the designed elements have more to 6000 phase variation that achieved by varying the length of the each elements. A thin dielectric substrate of thickness 0. 8mm placed above an air layer of 2mm is used. The reflectarray is center fed by a linearly polarized pyramidal horn antenna. The X band elements have-1dB gain bandwidth of about 17. 4% covering 11-13 GHz and the Ku band has about 13% bandwidth covering 12. 7-14. 5 GHz. The measured antenna gain at 11. 5 GHz is 23. 9 dB and at 14 GHz is 26. 1 dB showing aperture efficiency of 41% and 45%, respectively.

A new method for baseband demodulation of OQPSK has been proposed in this paper. The sampling rate is two times the Nyquist rate which is very low compared with similar demodulators. The demodulation process includes baseband mixer bank, matching filter, timing recovery and phase recovery. To fasten the process, we have used the fast convolution in matching filter. Besides, a new phase recovery method has been proposed which can be used in other phase demodulators such as QPSK. The high data rate demodulator will demodulate OQPSK with data rates ranging from 1 Mega-bits to more than 500 Mega-bits per second. The experiments show that this architecture can efficiently work with performance loss less than 0. 8dB for low SNR (i. e. Eb/N0≃ 5dB) and 0. 2 dB for high SNR (i. e. Eb/N0≃ 10dB).

Deployment method and arrangement of WSN deployment isone of the major challenges in designing wireless sensor networks and effective in their performance. Because coverage overlapping of nodes and on the contrary, development of hole coverage in their topology can result in decreasing strongly network efficiency & its length of life. This article offers a new & efficient distributive method for repairing hole coverage, whose work is based on node density after random deployment of nodes. The proposed algorithm (FHORA: Fuzzy Hole Repair Algorithm) considers limited ability of nodes in movement and can choose suitable mobile nodes according to their degree of coverage overlapping by using a fuzzy model. For repairing holecoverage, nodes move with high density & enough energy so that they can set network uniform density without increasing coverage degree of mobile node neighbors. The simulation results show that nodes movement in proposed method is less compared with the same protocol. Moreover; by this method, a significant amount of coverage overlapping can be minimized &the percent of coverage holes can be maximized.

In this paper, a wideband two-stage low-noise amplifier (LNA) is presented. The proposed architecture achieves wideband matching, low noise figure and high flat gain simultaneously by employing a negative-positive feedback technique. A common-gate input stage exploits a gm-boosting technique to achieve noise-reduction. In addition, a positive transformer feedback is used to add a degree of freedom in determining the transconductance of the impedance matching transistor. The proposed LNA has been designed and simulated using TSMC 0. 18-μ m standard RF CMOS process. Simulation results show that LNA achieves a return loss (S11) of below-10 dB, a noise figure (NF) of 2. 6– 3 dB, a flat power gain (S21) of 18± 0. 5 dB, and an IIP3 of 7 dBm, over a bandwidth of 6. 5– 10. 5 GHz. Designed LNA consumes 8 mW from a low power supply of 0. 85 V.

In this paper, a CAD tool based on the link between Hspice and a heuristic algorithm called Inclined Planes Optimization (IPO) is provided, which its goal is to obtain an optimal design for voltage comparators. This tool uses detailed models of transistors and considers all parasitic elements, to achieve solutions close to reality. The proposed CAD tool minimizes a multi-objective function and provides several 2-dimensional Pareto-fronts. Therefore, the designer understands the correlation between objective functions and selects the optimal design considering the application requirements. To evaluate the final results, 1000-run of Monte Carlo simulation and PVT verification design is performed.

The state of micro or nano-scale digital circuits will be suddenly changed in case of a charged particle collision and this leads to disturbances in the operation of the circuit and the circuit will fail. These particles in electrical harsh environments can induce different effects on the circuit which these effects may be temporary or permanent in terms of performance and type of circuit and the sensitivity of the circuit to charged particles will be increased by decreasing the dimensions of the circuit. Today the nano circuits are immunized against single events with specific technologies during design and implementation of these circuits. Due to a dramatic reduction in power consumption and circuit size, Quantum cellular automata have occupied a special place in nanoelectronic and utilizing the fault tolerance methods can improve the tolerability of these circuits in harsh environments. In this paper, we present a new method to increase the fault tolerance of QCA circuits and simulation of this method for the inverter logic gate in quantum cellular automata technology.

This paper is proposed a novel topology of a single phase grid connected inverter in order to conquest the common mode leakage current. There are many topologies presented so far, But none of them has the efficiency more than 98 percent. In this paper, a modern configuration is presented that, not only delete the common mode leakage current, but also increase the efficiency and power density and is affordable. this inverter consists of 6 switches and 2 diodes that in compare with similar ones, it has less element number. Than the famous topologies like H5, H6 and HERIC, the power loss and voltage stress on switches are decreased. These aspects are appears due to exclusive leg configuration and the placement of switches and diodes. The freewheel path revealed, decoupled DC side from AC side of Inverter which results in disconnecting the common mode current. This issue will modify the network reliability indices and maintain safety standards. Finally the performances of proposed inverter will be compared and evaluated with some available Inverters.

The purpose of this paper is designing a simple fabrication process to construct Al/SiO2 micro cantilever array based on bulk micro-machining technology. By the help of this process, bi-material cantilevers is implemented in a research laboratory with limited facilities. The results of this paper can be considered as the basis of designing and fabricating for Al/SiO2 micro cantilever sensors. Protection of Al in KOH, EDP and TMAH silicon etchant is the biggest technical problem of this type of micro cantilevers using bulk micromachining technique. In this method, Dual doped TMAH is used to fabricate micro cantilever. This process is realized with three single sides and one-double side lithography processes using two-chrome metal and one plastic transparent photomasks. Complexity of releasing the sacrificial layer is avoided using wet releasing of micro cantilever at ambient temperature. Then, Al/SiO2 micro cantilever array is fabricated with 50, 100, 150, 200, 250, 300, 350 and 400μ m lengths, 20 and 40μ m widths and 1μ m and 200nm thickness for SiO2 and Al, respectively.

The In-Band Full-Duplex (IBFD) technique is attracting a great deal of attention thanks to its ability to simultaneously transmit and receive the information over the same frequency band. IBFD has the potential to double the spectral efficiency and system capacity, compared to conventional Half-Duplex (HD) schemes. However, strong self-interference caused by simultaneous transmission and receiption over the same frequency band, renders the feasibility of IBFD in practice. Recently, advanced self-interference cancellation techniques are proposed to address this issue. In this paper, an IBFD relay network with Simultaneous Wireless Information and Power Transmission (SWIPT) is introduced that applies multiple relays. We propose a joint antenna-and-relay selection scheme that decreases the complexity and increases the ergodic capacity. We provide simulation results for the outage probability and the ergodic capacity. The results show that the IBFD system outperforms the HD system, for a certain range of self-interference power.

In this paper, design, simulation and fabrication of compact quad-band bandpass filters (BPF) using Split Ring Resonators (SRR) are presented. These types of filters are inherently narrow bandwidth. The bandwidths of the passbands of the filter are increased using an interdigital capacitor between two adjacent cells of the filter, and by increasing the substrate thickness. A quad-band BPF with center frequencies of 1. 5, 2. 24, 3. 07 and 4. 43 GHz was designed and simulation results show the bandwidths of these bands are 120, 219, 492 and 280 MHz respectively. In order to adjusting the center frequencies and their bandwidths for practical applications, parametric study and required simulations are presented. The proposed structure has sharp passband selectivity, acceptable insertion loss and return loss in each band, and controllable distance between the bands. Final filters (two structures) are implemented on Rogers 5870 substrate, and simulation and measured results are compared. Second fabricated filter has a compact size of that shows 18%, 69% and 43% size compacting in compare with three samples of quad-band filters of other references.

Speech recognition as one of the important branches of speech processing has been attractive for researchers and scientist, from long time ago. Speech recognition is a kind of technology able to determine the pronounced word (s) shown by acoustic signal. The complexity of speech recognition systems depends on the extracted features, their dimensions and the applied classifier. In this paper, we propose a new classifier which is able to compute two matrices “ winner” and “ minimum distance” in a knowledge extraction phase, as a suitable model for any reference word using synergy clustering and frequency of observations. In the recognition phase, the proposed method is able to determine the similarity between inputted unknown speech and word reference models based on a penalty-reward mechanism. In order to evaluate the proposed method, the FARSDAT data set is used. The results of several experiments on clean and noisy signals show more resistant against noise, higher accuracy and less time complexity for the proposed method, in comparison to the HMM-based speech recognition system.

Nowadays with the advancement of technology, the requirement for high speed circuits and memories with low leakage power consumption by keeping stability has been increased. In this paper, a stable 9T SRAM cell which is improved for high speed applications with low leakage power consumption has been suggested. In this scheme, two techniques including the isolation of read and write paths and the “ stack effect” technique are used simultaneously to improve read and write performance. The results of simulations in 32 nm CMOS technology indicate that the proposed cell is in the category of high speed cells. Meanwhile, the leakage power of the proposed cell has been reduced 16% to 48% compared with high speed cells. It should be noted that the read stability of the proposed cell has nearly become two times greater than the conventional 6T SRAM cell.

In this paper design and fabrication of an integrated electrooptical modulator in lithium niobate by proton exchange process is presented. In order to decrease the drive voltage of the modulator, and to use a simpler manufacturing process without complicated alignment systems, a common aluminum mask was used for fabrication of waveguide and electrodes that leads to zero spacing between electrode and waveguides. Also to reach impedance matching between signal source and load a tapering section was designed and fabricated. In addition, for design of different parts of modulator, numerical and analytical methods was used to calculate proton diffusion, refractive index change of the waveguide, light mode profile in waveguide, electric field profile of the electrodes and length and characteristics of transmission line.

Today static memories are one of important parts of digital circuits and due to appropriate speed and power are used to build embedded memories which are the SOC vital parts. Static memories are also used to create caches. With increased demand for battery driven applications, methods for reduce power consumption in the memory blocks receive special attention. Static memory cells are in hold mode most of the times, in addition when static memory size becomes large, static power will become significant and the most of power consumption will belong to it. Thus reduce static power becomes a priority. In this paper, a new low power SRAM with ability to separate read and write path is presented. The static power of proposed structure is reduced 78. 21% than the conventional six-transistor cell, and read static noise margin is enhanced 202. 59% rather than the conventional six-transistor cell. In order to evaluate the performance of the proposed cell and comparing the results, simulations are done in TSMC 130nm CMOS technology and the supply voltage of 1. 2 V.