This paper presents a new method for implementation of CMOS digital Fuzzy Logic Controller (FLC), which adds many analog design advantages such as low die area, high speed, and simplicity to the digital system. It also provides using more accurate methods such as product-sum for inference, center of area for defuzzifying and exploiting parallel strategy in digital FLC with no digital complexity and unchanged digital properties.
For implementing this idea, a programmable fuzzifier circuit has been designed based on a new strategy for a five-bit digital input signal and membership degree as an analog current with five-bit resolution in the range of 58uA. Membership functions which are generated by this membership function generator are trapezoidal and triangular capable of changing their ascending and descending slops arbitrarily, by controlling input digital parameters.
The inputs and single output of all system is digital while the interior blocks are mainly current-mode circuits. It has also been presented a new high-accurate simple current-mode circuit for Min-Max block. The systematical MATLAB simulations of the controller model and HSPICE circuit simulation in 0.35um CMOS standard process for a two-input one-singleton-output fuzzy controller with nine-rules have been presented. At last, the obtained characters are compared with the last previous works.