THE CSI JOURNAL ON COMPUTER SCIENCE AND ENGINEERING
Year:2006 | Volume:4 | Issue:3 (A)|Papers Count:5

Voice activity detection (VAD) has several applications in different areas of speech processing, as such speech recognition, speech compression and noise reduction. In this paper first, the related approaches presented in the literatures will be investigated. Next, a new procedure is proposed for distinguishing between silence and non-silence regions of a speech signal. The proposed technique is based on wavelet transform, because it provides a high capability of energy-separation in different sub bands. The obtained results confirm that the proposed method shows significant improvements in compare with other methods.

In this paper a very fast 4-2 compressor is introduced. Considering the fact that technological miniaturization is going to reach to its physical limits, there is no way except presenting new approaches and using new architectures. In this design we have improved the overall speed of the system using combined voltage and current mode circuits. All the simulation are done based on BSIMv3 and .25 urn technology. We have used Hspice and CosMos-Scope tools. The input patterns are generated and applied with MATLAB. According to the simulations, the proposed circuit has demonstrated significant improvement in terms of speed and power dissipation. The parameter used to compare the simulations reseals is PDP (power delay product). The other factor in order to compare these two designs is the number of transistors used. The proposed design illustrates 20% reduction in the transistor count.

Poet identification is a major branch of author identification, which is one important issue in text categorization and natural language processing. This paper discuses intelligent recognition of Shahnameh of Ferdowsi that uses feed-forward back-propagation (FF/BP) artificial neural networks (ANN). We also experiment the results of a decision tree system (DTS) for comparison. In poetic feature extraction phase, we try to simulate the human thinking about poem understanding and recognition. So we extract more than 64 data inputs from 22 various features which are categorized in physical, conceptual, and rhythmic classes. We have designed and implemented a special database of Persian words for quantitative measurement and examination of samples.According to the experimental results the DTS method achieved more than 85% of accuracy on classifying poems into the Shahnameh and non-Shahnameh classes, whereas ANN accomplished 100%. Afterward, to make an automatic feature reduction and determining usefulness of every poetic feature, we used a single Perception network. Combination of this network with the above methods keeps accuracy of classifiers, but decreases loadings of FF/BP-ANN.

The published timing attack schemes against modular exponentiation implementations are based on the large variations in their time measurements, while it is assumed that the running time of each step of the algorithm is independent of the running time of other steps. In this paper, we propose a new timing attack scheme against Blakley's modular multiplication, which has rather small timing variations with respect to modular exponentiation. We show that the assumption of independency of the running time of different steps is not valid for Blakley's algorithm. We mathematically model the correlations between the running times of different steps. It is assumed that a set of known inputs multiplied by the same constant and the running time of each multiplication are given, but the multiplication result is not known. In addition, a machine similar to victim machine is not available. In some applications, such as Digital Signature Standard, the constant is the secret key. We take advantage of the obtained correlation to present our timing attack scheme for obtaining the constant parameter, which is the secret key. In addition to the attack scheme, an error detection scheme is presented. We also propose an error correction method in order to improve our attack efficiency. Practical implementation of our attack against DSS shows that error probability is less than 0.15, and the 160-bit secret key is found using 1,500,000 timing measurements.

In this paper, we have proposed a novel hardware caching technique to reduce the communication latency in ODYSSEY methodology. The main idea is to implement small fast split caches in a parallel way to connect the medium to capture and store ownership information as the data flows from the memory module to the requesting processor. One of the main factors for estimating the rate of modem processors is their memory access time. Using cache memory enhances the access time; therefore it remarkably increases the rate. However, this rate is not sure enough for the systems like ODYSSEY which require parallel memory access time. In this paper, we present a new method in which cache memory is split into parts, so that simultaneous accesses to these parts are possible; therefore, the memory access time is highly improved.