Design and Implementation of an Intelligent High Frequency Counter with Optimized Architecture on a Low Cost FPGA Chip XC6SLX9-2FTG256C

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Keyhomayoon Sayyed Hossein; Amoom Mehdi

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Journal Paper

Paper Information

Journal: Journal of Intelligent Procedures in Electrical Technology Year:2023 | Volume:14 | Issue:54 Page(s): 147-157

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Information Journal Paper

Title

Design and Implementation of an Intelligent High Frequency Counter with Optimized Architecture on a Low Cost FPGA Chip XC6SLX9-2FTG256C

Author(s)

Keyhomayoon Sayyed Hossein | Amoom Mehdi | Issue Writer Certificate

Keywords

field-programmable gate array (FPGA) based time-to-digital convertor (TDC)

low cost FPGA

measurement accuracy

phased clocks

Abstract

In this paper, a 2 GHz counter is implemented on a low-cost XC6SLX9-2FTG256C field-programmable gate array (FPGA) chip from the Spartan6 family with a 500 ps resolution. Since the hardware resources contained in this chip are not sufficient to implement this design, and also the inherent delays of the hardware resources inside the chip are about few nanoseconds, achieving this accuracy is very important. The architecture used in this research is based on the phase difference clocks that has been implemented after optimization. To achieve this accuracy, it is necessary to design and implement counters with high clock frequency, low jitter and low skew, without dependence on hold time and setup time. Alternative hardware resources have also been used to compensate for the lack of hardware resources required to implement routing clocks.

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APA: Copy

Keyhomayoon, Sayyed Hossein, & Amoom, Mehdi. (2023). Design and Implementation of an Intelligent High Frequency Counter with Optimized Architecture on a Low Cost FPGA Chip XC6SLX9-2FTG256C. JOURNAL OF INTELLIGENT PROCEDURES IN ELECTRICAL TECHNOLOGY, 14(54 ), 147-157. SID. https://sid.ir/paper/1034862/en

Vancouver: Copy

Keyhomayoon Sayyed Hossein, Amoom Mehdi. Design and Implementation of an Intelligent High Frequency Counter with Optimized Architecture on a Low Cost FPGA Chip XC6SLX9-2FTG256C. JOURNAL OF INTELLIGENT PROCEDURES IN ELECTRICAL TECHNOLOGY[Internet]. 2023;14(54 ):147-157. Available from: https://sid.ir/paper/1034862/en

IEEE: Copy

Sayyed Hossein Keyhomayoon, and Mehdi Amoom, “Design and Implementation of an Intelligent High Frequency Counter with Optimized Architecture on a Low Cost FPGA Chip XC6SLX9-2FTG256C,” JOURNAL OF INTELLIGENT PROCEDURES IN ELECTRICAL TECHNOLOGY, vol. 14, no. 54 , pp. 147–157, 2023, [Online]. Available: https://sid.ir/paper/1034862/en

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