A NOVEL CMOS RIPPLE COMPARATOR CELL USING THE GATE- DIFFUSION INPUT TECHNIQUE

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KIANI SARKALEH A.; POURAHANGARYAN F.; NIARAKI ASLI R.

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Paper Information

Journal: Majlesi Journal of Electrical Engineering Year:2009 | Volume:3 | Issue:4 (11) Page(s): 69-74

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Title

A NOVEL CMOS RIPPLE COMPARATOR CELL USING THE GATE- DIFFUSION INPUT TECHNIQUE

Author(s)

KIANI SARKALEH A. | POURAHANGARYAN F. | NIARAKI ASLI R. | Issue Writer Certificate

Keywords

RIPPLE COMPARATORQ3

PROPAGATION DELAYQ3

LOW-POWERQ2

PDPQ3

GDIQ3

Abstract

In this paper a new implementation of CMOS RIPPLE COMPARATOR cell using the Gate-Diffusion Input (GDI) technique is presented. The proposed design using this technique allows for the reduction of power consumption, PROPAGATION DELAY, and the area of digital circuits while maintaining low complexity of logical design. The performance comparison with standard CMOS and GDI logic design techniques is presented. These methods are compared with respect to the number of devices, PDP, and power dissipation. Simulation results confirm that the proposed cell can work at low supply voltage and dissipates low power.

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APA: Copy

KIANI SARKALEH, A., POURAHANGARYAN, F., & NIARAKI ASLI, R.. (2009). A NOVEL CMOS RIPPLE COMPARATOR CELL USING THE GATE- DIFFUSION INPUT TECHNIQUE. MAJLESI JOURNAL OF ELECTRICAL ENGINEERING, 3(4 (11)), 69-74. SID. https://sid.ir/paper/188199/en

Vancouver: Copy

KIANI SARKALEH A., POURAHANGARYAN F., NIARAKI ASLI R.. A NOVEL CMOS RIPPLE COMPARATOR CELL USING THE GATE- DIFFUSION INPUT TECHNIQUE. MAJLESI JOURNAL OF ELECTRICAL ENGINEERING[Internet]. 2009;3(4 (11)):69-74. Available from: https://sid.ir/paper/188199/en

IEEE: Copy

A. KIANI SARKALEH, F. POURAHANGARYAN, and R. NIARAKI ASLI, “A NOVEL CMOS RIPPLE COMPARATOR CELL USING THE GATE- DIFFUSION INPUT TECHNIQUE,” MAJLESI JOURNAL OF ELECTRICAL ENGINEERING, vol. 3, no. 4 (11), pp. 69–74, 2009, [Online]. Available: https://sid.ir/paper/188199/en

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