ASYMMETRIC GATE OXIDE THICKNESS TECHNOLOGY FOR REDUCTION OF GATE INDUCED DRAIN LEAKAGE CURRENT IN NANOSCALE SINGLE GATE SOI MOSFET

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MOGHADASI M.N.; AHANGARI Z.

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Journal Paper

Paper Information

Journal: Majlesi Journal of Electrical Engineering Year:2009 | Volume:3 | Issue:2 (9) Page(s): 19-24

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Information Journal Paper

Title

ASYMMETRIC GATE OXIDE THICKNESS TECHNOLOGY FOR REDUCTION OF GATE INDUCED DRAIN LEAKAGE CURRENT IN NANOSCALE SINGLE GATE SOI MOSFET

Author(s)

MOGHADASI M.N. | AHANGARI Z. | Issue Writer Certificate

Keywords

BAND TO BAND TUNNELING (BTBT)Q3

GATE INDUCED DRAIN LEAKAGEQ3

DRAM CELLSQ3

Abstract

Gate Induced Drain Leakage (GIDL) current is one of the main leakage current components in Silicon on Insulator (SOI) MOSFET structure and plays an important role in the data retention time of DRAM CELLS. GIDL can dominate the drain leakage current at zero bias and will limit the scalability of the structure for low power applications. In this paper we propose a novel technique for reducing GIDL and hence off-state current in the nanoscale single gate SOI MOSFET structure. The proposed structure employs asymmetric gate oxide thickness, which can reduce GIDL current, and hence Ioff current to about 98% in comparison with the symmetric gate oxide thickness structure, without sacrificing the driving current and losing gate control over the channel. This technique is very simple in the fabrication point of view in CMOS technology.

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References

CHARACTERIZATION AND MODELING OF GATE-INDUCED-DRAIN-LEAKAGE

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APA: Copy

MOGHADASI, M.N., & AHANGARI, Z.. (2009). ASYMMETRIC GATE OXIDE THICKNESS TECHNOLOGY FOR REDUCTION OF GATE INDUCED DRAIN LEAKAGE CURRENT IN NANOSCALE SINGLE GATE SOI MOSFET. MAJLESI JOURNAL OF ELECTRICAL ENGINEERING, 3(2 (9)), 19-24. SID. https://sid.ir/paper/188257/en

Vancouver: Copy

MOGHADASI M.N., AHANGARI Z.. ASYMMETRIC GATE OXIDE THICKNESS TECHNOLOGY FOR REDUCTION OF GATE INDUCED DRAIN LEAKAGE CURRENT IN NANOSCALE SINGLE GATE SOI MOSFET. MAJLESI JOURNAL OF ELECTRICAL ENGINEERING[Internet]. 2009;3(2 (9)):19-24. Available from: https://sid.ir/paper/188257/en

IEEE: Copy

M.N. MOGHADASI, and Z. AHANGARI, “ASYMMETRIC GATE OXIDE THICKNESS TECHNOLOGY FOR REDUCTION OF GATE INDUCED DRAIN LEAKAGE CURRENT IN NANOSCALE SINGLE GATE SOI MOSFET,” MAJLESI JOURNAL OF ELECTRICAL ENGINEERING, vol. 3, no. 2 (9), pp. 19–24, 2009, [Online]. Available: https://sid.ir/paper/188257/en

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