Three-dimensional with the method mPL algorithm appropriate for improving the efficiency of Logic-on-Logic integrated circuits

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NASERI ALI; eyvazi mehdi

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Journal: ELECTRONIC INDUSTRIES Year:2019 | Volume:10 | Issue:2 Page(s): 81-86

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Title

Three-dimensional with the method mPL algorithm appropriate for improving the efficiency of Logic-on-Logic integrated circuits

Author(s)

NASERI ALI | eyvazi mehdi | Issue Writer Certificate

Keywords

Three-dimensional substitutionQ1

IntegratingQ1

PE moduleQ1

logic-on-logicQ1

AES moduleQ1

Abstract

Usually two-dimensional substitution is used for the production of integrated circuits. Due to heavy use of communications, two-dimensional substitution has high losses as well as, density of elements is low in it. To resolve this problem, Three-dimensional substitution method was proposed. Rather than the two-dimensional arrangement of elements in a row, elements are layout in three dimensions in this substitution. In this paper, Three-dimensional substitution algorithms using order used in two-dimensional substitution, Three-dimensional substitution analysis by mPL and Three-dimensional substitution simultaneous with two-dimensional substitution by mPL have been studied in terms of structure and function, and a butterfly processing element (PE) and an Advanced Encryption Standard (AES) block and a wireless MIMO decoder to assess them have been implemented with the mentioned methods. . Applying these methods shows that the use of face to face integration by microbuses in communications of substitution algorithm, on average, improves the maximum clock and block speed of AES encryption to 15. 3% and the maximum clock and block speed of PE module to 22. 6% as well as the maximum clock and speed of MIMO modules to 17. 1%, while the use of these methods has led to the average reduction in power consumption of 2. 6% for the AES module and the average reduction in power of 12. 9% for the PE module and the average reduction in power consumption of 5. 1% for MIMO module.

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APA: Copy

NASERI, ALI, & eyvazi, mehdi. (2019). Three-dimensional with the method mPL algorithm appropriate for improving the efficiency of Logic-on-Logic integrated circuits. ELECTRONIC INDUSTRIES, 10(2 ), 81-86. SID. https://sid.ir/paper/229588/en

Vancouver: Copy

NASERI ALI, eyvazi mehdi. Three-dimensional with the method mPL algorithm appropriate for improving the efficiency of Logic-on-Logic integrated circuits. ELECTRONIC INDUSTRIES[Internet]. 2019;10(2 ):81-86. Available from: https://sid.ir/paper/229588/en

IEEE: Copy

ALI NASERI, and mehdi eyvazi, “Three-dimensional with the method mPL algorithm appropriate for improving the efficiency of Logic-on-Logic integrated circuits,” ELECTRONIC INDUSTRIES, vol. 10, no. 2 , pp. 81–86, 2019, [Online]. Available: https://sid.ir/paper/229588/en

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