SELF AUTHENTICATION PATH INSERTION IN FPGA-BASED DESIGN FLOW FOR TAMPER-RESISTANT PURPOSE

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ZAMANZADEH SHARAREH; JAHANIAN ALI

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Paper Information

Journal: THE ISC INTERNATIONAL JOURNAL OF INFORMATION SECURITY Year:2016 | Volume:8 | Issue:1 Page(s): 53-60

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Title

SELF AUTHENTICATION PATH INSERTION IN FPGA-BASED DESIGN FLOW FOR TAMPER-RESISTANT PURPOSE

Author(s)

ZAMANZADEH SHARAREH | JAHANIAN ALI | Issue Writer Certificate

Keywords

FPGAQ2

HARDWARE SECURITYQ2

IP PROTECTIONQ2

SECURITY PATHQ2

Abstract

FPGA platforms have been widely used in many modern digital applications due to their low prototyping cost, short time-to-market and flexibility. Field-programmability of FPGA bitstream has made it as a flexible and easy-to-use platform. However, access to bitstream degraded the security of FPGA IPs because there is no efficient method to authenticate the originality of bitstream by the FPGA programmer. The issue of secure transmission of configuration information to the FPGAs is of paramount importance to both users and IP providers. In this paper we presented a "Self Authentication" methodology in which the originality of sub-components in bitstream is authenticated in parallel with the intrinsic operation of the design. In the case of discovering violation, the normal data flow is obfuscated and the circuit would be locked. Experimental results show that this methodology considerably improves the IP security against malicious updates with reasonable overheads.

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APA: Copy

ZAMANZADEH, SHARAREH, & JAHANIAN, ALI. (2016). SELF AUTHENTICATION PATH INSERTION IN FPGA-BASED DESIGN FLOW FOR TAMPER-RESISTANT PURPOSE. THE ISC INTERNATIONAL JOURNAL OF INFORMATION SECURITY, 8(1 ), 53-60. SID. https://sid.ir/paper/241799/en

Vancouver: Copy

ZAMANZADEH SHARAREH, JAHANIAN ALI. SELF AUTHENTICATION PATH INSERTION IN FPGA-BASED DESIGN FLOW FOR TAMPER-RESISTANT PURPOSE. THE ISC INTERNATIONAL JOURNAL OF INFORMATION SECURITY[Internet]. 2016;8(1 ):53-60. Available from: https://sid.ir/paper/241799/en

IEEE: Copy

SHARAREH ZAMANZADEH, and ALI JAHANIAN, “SELF AUTHENTICATION PATH INSERTION IN FPGA-BASED DESIGN FLOW FOR TAMPER-RESISTANT PURPOSE,” THE ISC INTERNATIONAL JOURNAL OF INFORMATION SECURITY, vol. 8, no. 1 , pp. 53–60, 2016, [Online]. Available: https://sid.ir/paper/241799/en

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