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Information Journal Paper

Title

RESEARCH NOTE: DESIGNING A RECONFIGURABLE ACCELERATOR

Pages

  75-84

Abstract

 Many of the video processing algorithms cannot be implemented in real time on general computers, due to their computational complexity. For an efficient implementation, a custom hardware that can be reconfigured for the algorithm, is used. In this paper a new acceleration hardware based on FPGA elements is proposed. This hardware can be adapted with the processing algorithm through FPGA design reconfiguration. Using a PCI slot, this hardware communicates with a Pc. The FPGAs are programmed through the PCI slot. The video frames are supplied to this hardware for processing. The performance of this hardware is evaluated using warping algorithms. The first and second order warping for a 512*512 frame can be done in 7.9 ms.

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  • Cite

    APA: Copy

    SEPYANI, A.A.R., KABIR, E.A., & BEHAZIN, F.. (2007). RESEARCH NOTE: DESIGNING A RECONFIGURABLE ACCELERATOR. MODARES TECHNICAL AND ENGINEERING, -(26 (SPECIAL ISSUE ON ELECTRICAL ENGINEERING)), 75-84. SID. https://sid.ir/paper/25050/en

    Vancouver: Copy

    SEPYANI A.A.R., KABIR E.A., BEHAZIN F.. RESEARCH NOTE: DESIGNING A RECONFIGURABLE ACCELERATOR. MODARES TECHNICAL AND ENGINEERING[Internet]. 2007;-(26 (SPECIAL ISSUE ON ELECTRICAL ENGINEERING)):75-84. Available from: https://sid.ir/paper/25050/en

    IEEE: Copy

    A.A.R. SEPYANI, E.A. KABIR, and F. BEHAZIN, “RESEARCH NOTE: DESIGNING A RECONFIGURABLE ACCELERATOR,” MODARES TECHNICAL AND ENGINEERING, vol. -, no. 26 (SPECIAL ISSUE ON ELECTRICAL ENGINEERING), pp. 75–84, 2007, [Online]. Available: https://sid.ir/paper/25050/en

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