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Cites:

Information Journal Paper

Title

DESIGN AND SIMULATION OF PIPELINED ADCS BASED ON LOW-VOLTAGE COMPARATORS

Pages

  87-98

Abstract

 In this paper, a PIPELINED ANALOG-TO-DIGITAL CONVERTER based on LOW-VOLTAGE COMPARATORS has been designed. The combination of a comparator and a CURRENT SOURCE as an alternative to op-amp, improved power efficiency and decreased complexity of design. For the first stage, capacitor GAIN DOUBLER is used as MDAC. Since the first stage cannot drive large capacitive loads, therefor a topology with high input impedance is chosen for the second, third and following stages. Besides, a modified cascode CURRENT SOURCE is used to obtain minimum overshoot at the output of stages. The ADC has been designed and simulated by HSPICE in a 90 nm CMOS process. Simulation results show that the ADC achieves 56.1 dB SNDR, 64.5 dB SFDR at 25MS/s and consumes 2 mW from a 1V power supply.

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  • Cite

    APA: Copy

    HOSSEINNEJAD, MAHDI, & SHAMSI, HOSSEIN. (2016). DESIGN AND SIMULATION OF PIPELINED ADCS BASED ON LOW-VOLTAGE COMPARATORS. TABRIZ JOURNAL OF ELECTRICAL ENGINEERING, 46(1 (75)), 87-98. SID. https://sid.ir/paper/256610/en

    Vancouver: Copy

    HOSSEINNEJAD MAHDI, SHAMSI HOSSEIN. DESIGN AND SIMULATION OF PIPELINED ADCS BASED ON LOW-VOLTAGE COMPARATORS. TABRIZ JOURNAL OF ELECTRICAL ENGINEERING[Internet]. 2016;46(1 (75)):87-98. Available from: https://sid.ir/paper/256610/en

    IEEE: Copy

    MAHDI HOSSEINNEJAD, and HOSSEIN SHAMSI, “DESIGN AND SIMULATION OF PIPELINED ADCS BASED ON LOW-VOLTAGE COMPARATORS,” TABRIZ JOURNAL OF ELECTRICAL ENGINEERING, vol. 46, no. 1 (75), pp. 87–98, 2016, [Online]. Available: https://sid.ir/paper/256610/en

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