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Information Journal Paper

Title

HIGH SPEED FULL SWING CURRENT MODE BICMOS LOGICAL OPERATORS

Pages

  211-220

Abstract

 In this paper the design of new high-speed current mode BICMOS logic circuits is proposed. By altering the THRESHOLD DETECTOR circuit of the conventional current mode logic circuits and applying the multiple value logic (MVL) approach the number of transistors in basic logic operators are significantly reduced and hence a reduction of chip area and power dissipation as well as an increase in speed is achieved. Simulation with HSpice using BSIM 3V3 model and experimental 65nm BICMOS technology were carried out for speed, and power consumption considerations at different supply voltage levels. Finally the performance of the proposed circuit is compared to an 8 bit voltage mode adder.

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    • Cite

    APA: Copy

    GHORBAN NIA DELAVAR, A., NAVI, K., & HASHEMIPOUR, O.. (2007). HIGH SPEED FULL SWING CURRENT MODE BICMOS LOGICAL OPERATORS. INTERNATIONAL JOURNAL OF ENGINEERING, 20(3 (TRANSACTIONS A: BASICS)), 211-220. SID. https://sid.ir/paper/355637/en

    Vancouver: Copy

    GHORBAN NIA DELAVAR A., NAVI K., HASHEMIPOUR O.. HIGH SPEED FULL SWING CURRENT MODE BICMOS LOGICAL OPERATORS. INTERNATIONAL JOURNAL OF ENGINEERING[Internet]. 2007;20(3 (TRANSACTIONS A: BASICS)):211-220. Available from: https://sid.ir/paper/355637/en

    IEEE: Copy

    A. GHORBAN NIA DELAVAR, K. NAVI, and O. HASHEMIPOUR, “HIGH SPEED FULL SWING CURRENT MODE BICMOS LOGICAL OPERATORS,” INTERNATIONAL JOURNAL OF ENGINEERING, vol. 20, no. 3 (TRANSACTIONS A: BASICS), pp. 211–220, 2007, [Online]. Available: https://sid.ir/paper/355637/en

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