Low-Power Register File Design in 90nm CMOS Technology

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Asyaei Mohammad

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Journal Paper

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Journal: Modeling in Engineering Year:2018 | Volume:16 | Issue:54 Page(s): 69-81

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Information Journal Paper

Title

Low-Power Register File Design in 90nm CMOS Technology

Author(s)

Asyaei Mohammad | Issue Writer Certificate

Keywords

Register fileQ1

dynamic circuitsQ1

localQ1

global bit linesQ1

noise immunityQ1

Abstract

The main portion of the power consumption in high speed Register files is related to read out paths which are implemented using the dynamic circuits. For this reason, a new dynamic circuit technique is proposed in this paper to reduce the power consumption of the Register files without significant speed and noise immunity degradation. In the proposed dynamic circuit, the pull down network is partitioned to the some smaller pull down networks to increase the circuit performance. Moreover, pull-down networks are precharged using NMOS transistors to reduce the voltage swing and hence decrease the power consumption. A 64-word x 32-bit 2-read, 1-write ported Register file is implemented using the proposed circuit technique. Simulation of Register files are performed using HSPICE simulator in low-Vth 90-nm CMOS technology model. Simulation results demonstrate 37% and 36% reduction in power and delay respectively at the same noise immunity compared to the conventional Register file.

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APA: Copy

Asyaei, Mohammad. (2018). Low-Power Register File Design in 90nm CMOS Technology. JOURNAL OF MODELING IN ENGINEERING, 16(54 ), 69-81. SID. https://sid.ir/paper/365018/en

Vancouver: Copy

Asyaei Mohammad. Low-Power Register File Design in 90nm CMOS Technology. JOURNAL OF MODELING IN ENGINEERING[Internet]. 2018;16(54 ):69-81. Available from: https://sid.ir/paper/365018/en

IEEE: Copy

Mohammad Asyaei, “Low-Power Register File Design in 90nm CMOS Technology,” JOURNAL OF MODELING IN ENGINEERING, vol. 16, no. 54 , pp. 69–81, 2018, [Online]. Available: https://sid.ir/paper/365018/en

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