Design and Simulation of a 8-Channel, Low-Power, and Small Chip-Area Neural Interfacing Chip

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MAGHAMI MOHAMMAD HOSSEIN; SODAGAR AMIR MASOUD

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Journal Paper

Paper Information

Journal: TABRIZ JOURNAL OF ELECTRICAL ENGINEERING Year:2020 | Volume:50 | Issue:1 (91) Page(s): 403-418

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Information Journal Paper

Title

Design and Simulation of a 8-Channel, Low-Power, and Small Chip-Area Neural Interfacing Chip

Author(s)

MAGHAMI MOHAMMAD HOSSEIN | SODAGAR AMIR MASOUD | Issue Writer Certificate

Keywords

Stimulation back-endQ1

exponential current stimulationQ1

indirect negative feedbackQ1

neural recording amplifiersQ1

current conveyor circuitsQ1

Abstract

This article reports on the design of a 8-channel neural recording amplifier and Stimulation back-end in TSMC 0. 18μ m technology which can do the recording and stimulating simultaneously. The design of proposed neural amplifier is based on indirect negative feedback and provides tunable lower cutoff frequency, and digitally-programmable upper cutoff frequency and voltage gain. Moreover, the proposed circuit employs attenuators in the same feedback loop in order to further reduce the silicon area consumed by the capacitors and at the same time to increase the input impedance of the circuit. The 8-channel designed circuit consumes 0. 27mm2 of chip area and operated with a supply voltage of 1. 8V, power consumption of each channel is 27μ W with the THD of-50dB@1kHz and output voltage swing of 0. 95Vpp. The designed stimulation bak-end circuit, in addition to traditional rectangular pulse shapes, can generates biphasic stimulation pulses with exponential shapes, whose time constants are digitally programmable. A class-B second generation current conveyor is designed to be used for delivering stimulation current pulses of up to ± 96μ A to the target tissue and a charge pump block is in charge of the generating supply voltages of ± 3. 3V. The circuit consumes 0. 043mm2 of silicon area for each channel (excluding charge pumps). Simulation results indicate that the stimuli generator meets expected requirements with the maximum power consumption of 1. 2mW when connected to electrode-tissue impedance of as high as 25kΩ .

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APA: Copy

MAGHAMI, MOHAMMAD HOSSEIN, & SODAGAR, AMIR MASOUD. (2020). Design and Simulation of a 8-Channel, Low-Power, and Small Chip-Area Neural Interfacing Chip. TABRIZ JOURNAL OF ELECTRICAL ENGINEERING, 50(1 (91) ), 403-418. SID. https://sid.ir/paper/404224/en

Vancouver: Copy

MAGHAMI MOHAMMAD HOSSEIN, SODAGAR AMIR MASOUD. Design and Simulation of a 8-Channel, Low-Power, and Small Chip-Area Neural Interfacing Chip. TABRIZ JOURNAL OF ELECTRICAL ENGINEERING[Internet]. 2020;50(1 (91) ):403-418. Available from: https://sid.ir/paper/404224/en

IEEE: Copy

MOHAMMAD HOSSEIN MAGHAMI, and AMIR MASOUD SODAGAR, “Design and Simulation of a 8-Channel, Low-Power, and Small Chip-Area Neural Interfacing Chip,” TABRIZ JOURNAL OF ELECTRICAL ENGINEERING, vol. 50, no. 1 (91) , pp. 403–418, 2020, [Online]. Available: https://sid.ir/paper/404224/en

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