مرکز اطلاعات علمی Scientific Information Database (SID) - Trusted Source for Research and Academic Resources

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Information Journal Paper

Title

HARDWARE IMPLEMENTATION OF 128-BIT AES IMAGE ENCRYPTION WITH LOW POWER TECHNIQUES ON FPGA

Pages

  13-22

Keywords

ADVANCED ENCRYPTION STANDARD (AES) 

Abstract

 This paper describes the implementation of a low power and high-speed encryption algorithm with high throughput for encrypting the image. Therefore, we select a highly secured symmetric key encryption algorithm AES (Advanced Encryption Standard), in order to decrease the power using retiming and GLITCH and operand isolation techniques in four stages, control unit based on logic gates, optimal design of multiplier blocks in mixcolumn phase and simultaneous production keys and rounds. Such procedure makes AES suitable for fast IMAGE ENCRYPTION.Implementation of a 128-bit AES on FPGA of Altera Company has been done, and the results are as follows: throughput, 6.5 Gbps in 441.5 MHz and 130mw power consumption. The time of encrypting in tested image with 32*32 sizes is 1.25ms.

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  • Cite

    APA: Copy

    FARMANI, ALI, & BALAZADEH BAHAR, HOSSEIN. (2012). HARDWARE IMPLEMENTATION OF 128-BIT AES IMAGE ENCRYPTION WITH LOW POWER TECHNIQUES ON FPGA. MAJLESI JOURNAL OF ELECTRICAL ENGINEERING, 6(4 (23)), 13-22. SID. https://sid.ir/paper/626719/en

    Vancouver: Copy

    FARMANI ALI, BALAZADEH BAHAR HOSSEIN. HARDWARE IMPLEMENTATION OF 128-BIT AES IMAGE ENCRYPTION WITH LOW POWER TECHNIQUES ON FPGA. MAJLESI JOURNAL OF ELECTRICAL ENGINEERING[Internet]. 2012;6(4 (23)):13-22. Available from: https://sid.ir/paper/626719/en

    IEEE: Copy

    ALI FARMANI, and HOSSEIN BALAZADEH BAHAR, “HARDWARE IMPLEMENTATION OF 128-BIT AES IMAGE ENCRYPTION WITH LOW POWER TECHNIQUES ON FPGA,” MAJLESI JOURNAL OF ELECTRICAL ENGINEERING, vol. 6, no. 4 (23), pp. 13–22, 2012, [Online]. Available: https://sid.ir/paper/626719/en

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