A NOVEL FIVE-TRANSISTOR SRAM CELL FOR HIGH SPEED AND HIGH DENSITY APPLICATIONS

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AZIZI MAZRAEH A.; MANZOURI M.T.

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Journal: THE CSI JOURNAL ON COMPUTER SCIENCE AND ENGINEERING Year:2008 | Volume:6 | Issue:1 (A) Page(s): 44-55

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Information Journal Paper

Title

A NOVEL FIVE-TRANSISTOR SRAM CELL FOR HIGH SPEED AND HIGH DENSITY APPLICATIONS

Author(s)

AZIZI MAZRAEH A. | MANZOURI M.T. | Issue Writer Certificate

Keywords

POSITIVE FEEDBACKQ3

CURRENT OF CELLQ3

READ STATIC NOISE MARGINQ3

WRITE OPERATIONQ3

READ OPERATIONQ3

ARRAY OF CELLSQ3

Abstract

To help overcome limits to the speed and density of conventional SRAMs, we have developed a five-transistor SRAM cell. The newly developed CMOS five-transistor SRAM uses one bit-line during read/write operation. This cell retains its data with leakage current and POSITIVE FEEDBACK without refresh cycle. The new cell size is 18% smaller than a conventional six-transistor cell using same design rules. Simulation results obtained from HSPICE 2008 in 0.25mm technology show new cell is 27% faster than conventional six-transistor cell. Furthermore, the analytical results are in good agreement with the improvement of speed in new cell.

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APA: Copy

AZIZI MAZRAEH, A., & MANZOURI, M.T.. (2008). A NOVEL FIVE-TRANSISTOR SRAM CELL FOR HIGH SPEED AND HIGH DENSITY APPLICATIONS. THE CSI JOURNAL ON COMPUTER SCIENCE AND ENGINEERING, 6(1 (A)), 44-55. SID. https://sid.ir/paper/70686/en

Vancouver: Copy

AZIZI MAZRAEH A., MANZOURI M.T.. A NOVEL FIVE-TRANSISTOR SRAM CELL FOR HIGH SPEED AND HIGH DENSITY APPLICATIONS. THE CSI JOURNAL ON COMPUTER SCIENCE AND ENGINEERING[Internet]. 2008;6(1 (A)):44-55. Available from: https://sid.ir/paper/70686/en

IEEE: Copy

A. AZIZI MAZRAEH, and M.T. MANZOURI, “A NOVEL FIVE-TRANSISTOR SRAM CELL FOR HIGH SPEED AND HIGH DENSITY APPLICATIONS,” THE CSI JOURNAL ON COMPUTER SCIENCE AND ENGINEERING, vol. 6, no. 1 (A), pp. 44–55, 2008, [Online]. Available: https://sid.ir/paper/70686/en

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