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Information Journal Paper

Title

PROCESS-VARIATION-A WARE INSTRUCTION RESCHEDULING TO REDUCE LEAKAGE IN NANOMETER INSTRUCTION CACHES

Pages

  16-24

Abstract

PROCESS VARIATION, despite introducing challenges in stability and power of SRAM memories, provides a new opportunity for leakage-power reduction: statistical simulation shows that the same SRAM cell leaks differently when storing 0 and 1; this difference is as high as 57% at 60mv variation of threshold voltage (Vth). Thus, leakage can be reduced if values with less leakage can be stored in the cells. We show applicability of this proposal by presenting a first technique for reducing INSTRUCTION CACHE leakage: we reorder instructions within basic-blocks so as to match up the instructions with the less-leaky state of their corresponding cache cells.Experimental results show up to 12.51%, averaging 10.73%, leakage energy reduction at 60mv variation in Vth, and that this saving increases with technology scaling. Since intra-basic-block rescheduling does not affect INSTRUCTION CACHE hit ratio, this reduction is provided with only a negligible penalty, in rare cases, in the data cache.

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    APA: Copy

    GOUDARZI, MAZIAR, & ISHIHARA, TOHRU. (2008). PROCESS-VARIATION-A WARE INSTRUCTION RESCHEDULING TO REDUCE LEAKAGE IN NANOMETER INSTRUCTION CACHES. THE CSI JOURNAL ON COMPUTER SCIENCE AND ENGINEERING, 5(2-4 (B)), 16-24. SID. https://sid.ir/paper/70717/en

    Vancouver: Copy

    GOUDARZI MAZIAR, ISHIHARA TOHRU. PROCESS-VARIATION-A WARE INSTRUCTION RESCHEDULING TO REDUCE LEAKAGE IN NANOMETER INSTRUCTION CACHES. THE CSI JOURNAL ON COMPUTER SCIENCE AND ENGINEERING[Internet]. 2008;5(2-4 (B)):16-24. Available from: https://sid.ir/paper/70717/en

    IEEE: Copy

    MAZIAR GOUDARZI, and TOHRU ISHIHARA, “PROCESS-VARIATION-A WARE INSTRUCTION RESCHEDULING TO REDUCE LEAKAGE IN NANOMETER INSTRUCTION CACHES,” THE CSI JOURNAL ON COMPUTER SCIENCE AND ENGINEERING, vol. 5, no. 2-4 (B), pp. 16–24, 2008, [Online]. Available: https://sid.ir/paper/70717/en

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