مرکز اطلاعات علمی Scientific Information Database (SID) - Trusted Source for Research and Academic Resources

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Information Journal Paper

Title

Design of a 16-by-16-bit Unsigned Serial-parallel Multiplier using Retime Technique

Pages

  49-58

Abstract

 In this paper, the structure of a 16-by-16 Unsigned hybrid (Serial-Parallel) Multiplier has been proposed. Parallel Multipliers, in comparison with serial Multipliers, have higher speed and higher power consumption. In hybrid structures, to reduce power and increase speed, both serial and parallel techniques are used. The proposed structure improves propagation delay and reduces power consumption using Pipeline and Retime techniques. Simulation results show that it has 5. 7 ns propagation delay and 2. 65 mW power consumption. The figure of merit for energy consumption is 15. 2 PJ. The proposed Multiplier has been designed using 0. 18 μ m TSMC process at 1. 8 V supply and simulated using Cadence tools. The layout of the Multiplier occupies 52414 μ m 2.

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    • Cite

    APA: Copy

    Vafi, Amirhossien, Daie Kozehkanani, Ziaddin, Sobhi, Jafar, & Yousefi, Mousa. (2020). Design of a 16-by-16-bit Unsigned Serial-parallel Multiplier using Retime Technique. MAJLESI JOURNAL OF ELECTRICAL ENGINEERING, 14(1), 49-58. SID. https://sid.ir/paper/741958/en

    Vancouver: Copy

    Vafi Amirhossien, Daie Kozehkanani Ziaddin, Sobhi Jafar, Yousefi Mousa. Design of a 16-by-16-bit Unsigned Serial-parallel Multiplier using Retime Technique. MAJLESI JOURNAL OF ELECTRICAL ENGINEERING[Internet]. 2020;14(1):49-58. Available from: https://sid.ir/paper/741958/en

    IEEE: Copy

    Amirhossien Vafi, Ziaddin Daie Kozehkanani, Jafar Sobhi, and Mousa Yousefi, “Design of a 16-by-16-bit Unsigned Serial-parallel Multiplier using Retime Technique,” MAJLESI JOURNAL OF ELECTRICAL ENGINEERING, vol. 14, no. 1, pp. 49–58, 2020, [Online]. Available: https://sid.ir/paper/741958/en

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