ANALYTICAL EVALUATION OF A NEW ERROR DETECTION SCHEME

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RAJABZADEH amir; Mohandespour Mirzad; Miremadi Ghassem

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Seminar Paper

Paper Information

Seminar: CONFRANCE SALANE ANJOMANE COMPUTER IRAN
Year:2004 | Issue:9

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Title

ANALYTICAL EVALUATION OF A NEW ERROR DETECTION SCHEME

Author(s)

RAJABZADEH amir | Mohandespour Mirzad | Miremadi Ghassem

Keywords

COTS PROCESSORS

FAULT INJECTION

ERROR DETECTION COVERAGE

PERFORMANCE MONITORING

ANALYTICAL EVALUATION

Abstract

INCREASING USE OF COMMERCIAL OFF-THE-SHELF (COTS) SUPERSCALAR PROCESSORS IN INDUSTRIAL, EMBEDDED, AND REAL-TIME SYSTEMS NECESSITATES THE DEVELOPMENT OF ERROR DETECTION MECHANISMS FOR SUCH SYSTEMS. THIS PAPER PRESENTS AN ERROR DETECTION SCHEME CALLED COMMITTED INSTRUCTIONS COUNTING (CIC) TO INCREASE ERROR DETECTION IN COTS SUPERSCALAR PROCESSORS. THE SCHEME IS ANALYTICALLY EVALUATED BASED ON PROBABILISTIC MODELS OF CONTROL FLOW ERRORS (CFES). THE RESULTS SHOW THAT THE MINIMUM ERROR DETECTION COVERAGE VARIES BETWEEN TO 92.16% AND 96.29%, FOR DIFFERENT WORKLOADS.

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APA: Copy

RAJABZADEH, amir, Mohandespour, Mirzad, & Miremadi, Ghassem. (2004). ANALYTICAL EVALUATION OF A NEW ERROR DETECTION SCHEME. Confrance Salane Anjomane Computer Iran. SID. https://sid.ir/paper/905590/en

Vancouver: Copy

RAJABZADEH amir, Mohandespour Mirzad, Miremadi Ghassem. ANALYTICAL EVALUATION OF A NEW ERROR DETECTION SCHEME. 2004. Available from: https://sid.ir/paper/905590/en

IEEE: Copy

amir RAJABZADEH, Mirzad Mohandespour, and Ghassem Miremadi, “ANALYTICAL EVALUATION OF A NEW ERROR DETECTION SCHEME,” presented at the Confrance Salane Anjomane Computer Iran. 2004, [Online]. Available: https://sid.ir/paper/905590/en

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