CPU caches are powerful sources of information leakage. To develop practical cache-based attacks, the need for automation of the process of finding exploitable cachebased side-channels in computer systems is felt more than ever. Cache template attack is a generic technique that utilizes Flush+Reload attack in order to automatically exploit cache vulnerability of Intel platforms. Cache template attack on the T-table-based AES implementation consists of two phases including the pro, ling phase and key exploitation phase. Pro, ling is a preprocessing phase to monitor dependencies between the secret key and behavior of the cache memory. In addition, the addresses of T-tables can be obtained automatically. At the key exploitation phase, Most Significant Bits (MSBs) of the secret key bytes are retrieved by monitoring the exploitable addresses. This study proposed a simple yet effective searching technique, which accelerates the pro, ling phase by a factor of utmost 64. In order to verify the theoretical model of our technique, the mentioned attack on AES was implemented. The experimental results revealed that the pro, ling phase runtime of the cache template attack was approximately 10 minutes, while the proposed method could speed up the running of this phase up to almost 9 seconds.

In cloud computing, multiple users can share the same physical machine that can potentially leak secret information, in particular when the memory de-duplication is enabled. Flush+Reload attack is a cache-based attack that makes use of resource sharing. T-table implementation of AES is commonly used in the crypto libraries like OpenSSL. Several Flush+Reload attacks on T-table implementation of AES have been proposed in the literature which requires a notable number of encryptions. In this paper, we present a technique to enhance the Flush+Reload attack on AES in the ciphertext-only scenario by significantly reducing the number of needed encryptions in both native and cross-VM setups. In this paper, we focus on finding the wrong key candidates and keep the right key by considering only the cache miss event. Our attack is faster than previous Flush+Reload attacks. In particular, our method can speed-up the Flush+Reload attack in cross-VM environment significantly. To verify the theoretical model, we implemented the proposed attack.

Critical theory has always been unders tood by contemporary philosophy and sociology as something definite and “known” that finds its main roots in Hegelian-Marxis t negation. But less attention has been paid to the ques tion of whether other lineages and societies can be discovered or “invented” for it? Leibniz can be considered a philosopher who, through the lens of his differential philosophy, exerted a marginal but powerful influence on critical theory. Here it is shown how the three AES thetic concepts: Inequality, Autonomy and Harmony, are rooted in a kind of differential calculus and can be explained using concepts such as Identity, Monad and Com-Possibility. In addition to identifying the Leibnizian roots of negative AES thetics, the ques tion has also been raised as to how these concepts relate to differential concepts. Apart from the concept of Inequality in Adorno’s thought, which is somehow in antagonis tic relation to the Principle of Identity, the other two concepts can be considered as philosophical-AES thetic forms of mathematical-physical concepts,In a way, the Autonomic Art was shown to be a kind of monad, and Harmony was shown as a form of Continuity. The idea of ​​how a philosophical theory can be inspired by new mathematics or physics should be considered the mos t promising achievement of this research.

MP-AES is the ideal instrument for people looking to transition from Flame Atomic Absorption Spectroscopy (FAAS) to another technique. By using nitrogen as the source gas for the plasma, running costs are greatly reduced, and by removing the requirement for hazardous nitrous oxide and acetylene safety is greatly increased. Additionally the higher temperature nitrogen plasma atomization/ ionization source improves detection limits, linear range, and long term stability, and allow the sample preparation process to be greatly simplified.

This paper introduces a high-Speed fault-resistant hardware implementation for the S-box of AES cryptographic algorithm, called HFS-box. A deep pipelining for S-box at the gate level is proposed. In addition, in HFS-box a new Dual Modular Redundancy based (DMR-based) countermeasure is exploited for fault correction purpose. The newly introduced countermeasure is a fault correction scheme based on DMR technique (FC-DMR) combined with a version of the time redundancy technique. In the proposed architecture, when a transient random or malicious fault(s) is detected in each pipeline stage, the error signal corresponding to that stage becomes high. The control unit holds the previous correct value in the output of our proposed DMR voter in the other pipeline stages as soon as it observes the value ‘1’ on the error signal. The previous correct outputs will be kept until the fault effect disappears. The presented low-cost HFS-box provide a high capability of fault resistance against transient faults with any duration by imposing low area overhead compared with similar fault correction strategies, i.e. 137%, and low throughput degradation, i.e. 11.3%, on the original S-box implementation.

Side-channel attacks are considered to be the most important problems of modern digital security systems. Today, Differential Power Attack (DPA) is one of the most powerful tools for attacking hardware encryption algorithms in order to discover the correct key of the system. In this work, a new scheme based on randomizing power consumption of a fixed-operation logic gate is proposed. The goal of this method is enhancing the immunity of AES algorithm against DPA. Having a novel topology to randomize the power consumption of each Exclusive-NOR gate, the proposed circuit causes random changes in the overall power consumption of the steps of the algorithm; thus, the correlation between the instantaneous power consumption and the correct key is decreased and the immunity of the AES implementations which the key is injected into their process through Exclusive-NOR gates is extremely increased. The proposed method can be used as a general hardening method in the majority of cryptographic algorithms. The results of theoretical analysis and simulations in 90-nm technology demonstrate the capability of the proposed circuits to strengthen AES against DPA. The CMOS area and power consumption overhead is less than 1%.

Masking techniques are used to protect the hardware implementation of cryptographic algorithms against side-channel attacks. Reconfigurable hardware, such as FPGA, is an ideal target for the secure implementation of cryptographic algorithms. Due to the restricted resources available to the reconfigurable hardware, efficient secure implementation is crucial in an FPGA. In this paper, a two-share threshold technique for the implementation of AES is proposed. In continuation of the work presented by Shahmirzadi et al. at CHES 2021, we employ built-in Block RAMs (BRAMs) to store component functions. Storing several component functions in a single BRAM may jeopardize the security of the implementation. In this paper, we describe a sophisticated method for storing two separate component functions on a single BRAM to reduce area complexity while retaining security. Out design is well suited for FPGAs, which support both encryption and decryption. Our synthesis results demonstrate that the number of BRAMs used is reduced by 50% without affecting the time or area complexities.