Different factors such as nonlinear phenomena and mode instability affect the output of the high-power fiber lasers and AMPLIFIERs. Since these devices have many applications in the industry, medicine, and military facilities, the study of the various factors’ effects on their output is directly reflected on the design of high-power lasers and AMPLIFIERs. In the present paper, the mode instability which is the major limiting factor on the output of high power lasers and AMPLIFIERs has been studied, simulated, and investigated. In these high-power devices, the temperature increases due to quantum defects, background loss, and light scattering, which change the refractive index of the fiber material. Variation of the refractive index is the main reason of mode instability in high power fiber lasers and AMPLIFIERs. Mode instability causes the coupling of the fundamental mode to the upper-mode and thus decreases the fundamental mode’ s energy. In this paper, different factors that affect the threshold of the mode instability and power transfer from the fundamental mode to the upper mode have been investigated.

A new output structure for class E power AMPLIFIER (PA) is proposed in this paper. A series LC resonator circuit, tuned near the second harmonic of the operating frequency is added to the output circuit. This resonator causes low impedance at the second harmonic. The output circuit is designed to shape the switch voltage of the class E AMPLIFIER and lower the voltage stress of the transistor. The maximum switch voltage of the conventional class E PA is 3.56Vdc. However, higher switch voltage of about 4.5VDC may be occurred, by considering nonlinear drain-to-source capacitance in class E PA. The obtained peak switch voltage of the designed class E PA is approximately 75% of the conventional one with the same conditions, which shows a significant reduction in peak switch voltage. MOSFET parasitic nonlinear gate-to-drain and nonlinear drain-to-source capacitances of the MOSFET body junction diode also affect the switch voltage in class E PA, which are considered in this paper. The actual MOSFETs have these parasitic capacitances; therefore, it is necessary to consider these elements in the design procedure. Reduced switch voltage in class E PA relaxes the breakdown voltage constraints of the active device. In the switch voltage of the designed circuit, the zero voltage and zero derivative switching (ZVS and ZVDS) conditions are satisfied. Simulation of the presented circuit is performed using PSpice and LTspice softwares. For verification of the designed circuit, the presented PA is fabricated and measured.

Background and Objectives: In this paper, a novel structure as a Folded-Mirror (FM) Trans-impedance AMPLIFIER (TIA) is designed and introduced for the first time based on the combination of the current-mirror and the folded-cascade topologies. The trans-impedance AMPLIFIER stage is the most critical building block in a receiver system. This novel proposed topology is based on the combination of the current mirror topology and the folded-cascade topology, which is designed using active elements. The idea is to use a current mirror topology at the input node. In the proposed circuit, unlike many other reported designs, the signal current (and not the voltage) is being amplified till it reaches the output node. The proposed TIA benefits from a low input resistance, due to the use of a diode-connected transistor, as part of the current mirror topology, which helps to isolate the dominant input capacitance. So, as a result, the data rate of 5Gbps is obtained by consuming considerably low power. Also, the designed circuit employs only six active elements, which yields a small occupied chip area, while providing 40.6dBΩ of trans-impedance gain, 3.55GHz frequency bandwidth, and 664nArms input-referred noise by consuming only 315µW power using a 1V supply. Results justify the proper performance of the proposed circuit structure as a low-power TIA stage.Methods: The proposed topology is based on the combination of the current mirror topology and the folded-cascade topology. The circuit performance of the proposed folded-mirror TIA is simulated using 90nm CMOS technology parameters in the Hspice software. Furthermore, the Monte-Carlo analysis over the size of widths and lengths of the transistors is performed for 200runs, to analyze the fabrication process.Results: The proposed FM TIA circuit provides 40.6dBΩ trans-impedance gain and 3.55GHz frequency bandwidth, while, consuming only 315µW power using a 1V supply. Besides, as analyzing the quality of the output signal in the receiver circuits for communication applications is vital, the eye-diagram of the proposed FM TIA for a 50µA input signal is opened about 5mV, while, for a 100µA input signal the eye is opened vertically about 10mV. So, the vertical and horizontal opening of the eye is clearly shown. Furthermore, Monte-Carlo analysis over the trans-impedance gain represents a normal distribution with the mean value of 40.6dBΩ and standard deviation of 0.4dBΩ. Also, the value of the input resistance of the FM TIA is equal to 84.4Ω at low frequencies and reaches the value of 75Ω at -3dB frequency. The analysis of the effect of the feedback network on the value of the input resistance demonstrates the input resistance in the absence of the feedback network reaches up to 1.4MΩ, which yields the importance of the existence of the feedback network to obtain a broadband system.Conclusion: In this paper, a trans-impedance AMPLIFIER based on a combination of the current-mirror topology and the folded-cascade topology is presented, which amplifies the current signal and converts it to the voltage at the output node. Due to the existence of a diode-connected transistor at the input node, the input resistance of the TIA is comparatively small. Furthermore, four out of six transistors are PMOS transistors, which represent less thermal noise in comparison with NMOS transistors. Also, the proposed Folded-Mirror topology occupies a relatively small area on-chip, due to the fact that no passive element is used in the feedforward network. Results using 90nm CMOS technology parameters show 40.6dBΩ trans-impedance gain, 3.55GHz frequency bandwidth, 664nArms input-referred noise, and only 315µW power dissipation using a 1volt supply, which indicates the proper performance of the proposed circuit as a low-power building block.

A novel technique for a self-equalized distributed AMPLIFIER is presented by showing the analogy between transversal filters and distributed AMPLIFIER topologies. The appropriate delay and gain coefficients of AMPLIFIER circuit are obtained by a Fourier expansion of the raised cosine spectrum in the frequency range of 0-40GHz.

In this paper a new method for the design of a linear phase distributed AMPLIFIER in 180nm CMOS technology is presented. The method is based on analogy between transversal filters and distributed AMPLIFIERs topologies. In the proposed method the linearity of the phase at frequency range of 0-50 GHz is obtained by using proper weighting factors for each gain stage in cascaded AMPLIFIER topology. These weighting factors have been extracted using MATLAB software. Finally, by plotting the frequency response of the AMPLIFIER resulted from MATLAB code and also simulation from ADS, the phase linearity of the designed AMPLIFIER is shown.