The densely packed decimal (DPD) encoding for secondary and primary storage of three binary coded decimal (BCD) digits is included in the IEEE 754-2019 standard for decimal floating-point arithmetic. Binary coded chiliad (BCC) representation of 3 BCD digits (i. e. radix-1000) will achieve equiefficient packing. The primary advantage is BCC operands can be directly manipulated by arithmetic operations, while DPD operands have to undergo DPD-to-BCD and reverse conversions afore and ahead of each arithmetic operation. Therefore, we are interested in designing the arithmetic unit that receives BCC operands and produces BCC results, following previous BCC works. Compared to the equivalent BCD or other radix-10 arithmetic, prospects show that equally efficient arithmetic units are feasible for BCC arithmetic, as even better performance has been achieved in the case of addition. Therefore, we demonstrate the IEEE 754-2019 compatibility of the BCC Encoding in this paper. Consequently, for the DPD-to-BCD expansion and the reverse compression, the DPD-to-BCC converter, and the reverse blocks, we show the delay, area, and power dissipation. The findings show a substantial delay (83%), area (27%), and power (29%) overhead. However, as the number of conversions in the latter case is much less than the former, overall power dissipation is expected to decrease considerably.