Today power consumption is considered to be one of the important issues. Therefore, its reduction plays a considerable role in developing systems. Previous studies have shown that approximately 50% of total power consumption is used in Cache memories. There is a direct relationship between power consumption and replacement quantity made in Cache. The less the number of replacements is, the less the power consumption is. In this paper, a mechanism was proposed a mechanism to reduce power consumption using full associative organization and layered replacement algorithm. In this scheme, all Cache blocks were divided into three layers. Final layer used FIFO replacement algorithm and middle layer used random replacement algorithm. Also first layer used LRU replacement algorithm. Simulation results were shown using tools written by VB language that in the proposed plan the number of replacement was less than 8-way associative using LRU replacement algorithm.

The overall performance of any integrated circuit is defined by its proper memory design, as it is a mandatory and major block which requires more area and power. The prime interest of this article is to design a memory structure which is tolerant to variations in CNFET (Carbon nanotube field effect transistor) parameters like pitch, diameter and number of CNT tubes, and also offer low power and high speed of operation. In this context, CNFET based stacked SRAM (Static random access memory) design is proposed to attain the above mentioned criteria. Concept of stack effect is utilized in the cross coupled inverter section of the memory structure to attain low power. The power, speed and energy analysis for the proposed structure is done, and compared with the conventional structures to justify the proposed memory cell performance. HSPICE simulation results has confirmed that the proposed structure offers about 34%, 54% and 95% power saving in hold mode, read mode and write mode respectively. In speed and energy point of view it provides about 97% read delay, 92% write delay and 98% energy savings than the conventional memory structures. These results make it clear that the proposed SRAM is suitable for the 5G networks where circuit speed, power and energy consumption are the major concern.

The overall performance of any integrated circuit is defined by its proper memory design, as it is a mandatory and major block which requires more area and power. The prime interest of this article is to design a memory structure which is tolerant to variations in CNFET (Carbon nanotube field effect transistor) parameters like pitch, diameter and number of CNT tubes, and also offer low power and high speed of operation. In this context, CNFET based stacked SRAM (Static random access memory) design is proposed to attain the above mentioned criteria. Concept of stack effect is utilized in the cross coupled inverter section of the memory structure to attain low power. The power, speed and energy analysis for the proposed structure is done, and compared with the conventional structures to justify the proposed memory cell performance. HSPICE simulation results has confirmed that the proposed structure offers about 34%, 54% and 95% power saving in hold mode, read mode and write mode respectively. In speed and energy point of view it provides about 97% read delay, 92% write delay and 98% energy savings than the conventional memory structures. These results make it clear that the proposed SRAM is suitable for the 5G networks where circuit speed, power and energy consumption are the major concern.

CPU Caches are powerful sources of information leakage. To develop practical Cache-based attacks, the need for automation of the process of finding exploitable Cachebased side-channels in computer systems is felt more than ever. Cache template attack is a generic technique that utilizes Flush+Reload attack in order to automatically exploit Cache vulnerability of Intel platforms. Cache template attack on the T-table-based AES implementation consists of two phases including the pro, ling phase and key exploitation phase. Pro, ling is a preprocessing phase to monitor dependencies between the secret key and behavior of the Cache memory. In addition, the addresses of T-tables can be obtained automatically. At the key exploitation phase, Most Significant Bits (MSBs) of the secret key bytes are retrieved by monitoring the exploitable addresses. This study proposed a simple yet effective searching technique, which accelerates the pro, ling phase by a factor of utmost 64. In order to verify the theoretical model of our technique, the mentioned attack on AES was implemented. The experimental results revealed that the pro, ling phase runtime of the Cache template attack was approximately 10 minutes, while the proposed method could speed up the running of this phase up to almost 9 seconds.