In this article, the high-k gate dielectric effect on the operation of complementary metal oxide semiconductor (CMOS) inverter build using conventional (CL) double-gate (DG) metal oxide semiconductor field effect transistor (MOSFET) and junctionless (JL) double-gate (DG) MOSFET has been explored. It is found that the improvement in inverter performance is more pronounced in CL-DG-MOSFET based CMOS inverter in comparison to JL-DG-MOSFET based CMOS inverter when SiO2 is replaced by the high-k dielectric at gate oxide. The improvement in low noise margin (Δ, NML), high noise margin (Δ, NMH), gain (Δ, A) & propagation delay (Δ, Pd) is 3. 19%, 1. 64%, 5. 2% & 0. 9% respectively when SiO2 is replaced by TiO2 at gate oxide in case of CL-DG-MOSFET based CMOS inverter whereas it is 1. 96%, 1. 24%, 3. 4% & 1. 71% respectively in case of JLDG-MOSFET based CMOS inverter. Consequently, the utilization of high-k dielectric as gate oxide is more advantageous in CL-DG-MOSFET devices for improved stability and gain of CMOS inverter.