Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs) are commonly used as a synthesizer or clock and data recovery circuit in most of the communication systems. In this paper, a new DLL is designed based on PRP conjugate gradient algorithm. The proposed DLL do not need any phase frequency detector, charge pump and loop filters, hence it can contribute better jitter performance and higher speed in comparison with conventional DLLs. In this design, PRP conjugate gradient algorithm is used to optimize the delay amount of each delay cells therefore helps the DLL to lock more accurately and quickly compared with gradient algorithm. In addition, for applying the PRP conjugate gradient algorithm a digital signal processor is used in the proposed architecture. To show the accuracy of the proposed structure’s operation, simulation has been done for 15 delay cells and fREF is chosen 14MHz to have output frequency 14×15=210MHz. fOUT=210 MHz is one of the channels in Iran VHF frequency band. As shown with simulation, the proposed architecture has a locking time of approximately 286nsec which is equal to 4 clock cycles of the reference clock.

Triple-negative breast cancer (TNBC) is the most aggressive and heterogeneous cancer subtypes. High rates of metastasis, poor prognosis, and drug resistance are the major problems associated with TNBC. The current chemotherapeutics eliminate only the bulk tumor cells (non-BCSCs) and do not affect breast cancer stem cells (BCSCs). The BCSCs which are left behind after chemotherapy is reported to promote recurrence and metastasis of TNBC. Death receptor-5 (DR-5) is exclusively expressed in TNBCs and mediates the extrinsic pathway of apoptosis. DR-5, therefore, can be exploited for targeted drug delivery and to induce apoptosis. Gammasecretase mediated Notch signaling in BCSCs regulates its proliferation, differentiation, and metastasis. The endogenous ligand, delta-like ligand 4 (DLL4), is reported to activate this Notch signaling in TNBC. Blocking this signaling pathway using both gamma-secretase inhibitors (GSIs) and DLL4 monoclonal antibody (mAb) may produce synergistic benefits. Further, the GSIs (DAPT, LY-411575, RO4929097, MK0752, etc. ) suffer from poor bioavailability and off-target side effects such as diarrhea, suppression of lymphopoiesis, headache, hypertension, fatigue, and ventricular dysfunctions. In this hypothesis, we discuss solid lipid nanoparticles (SLNs) based drug delivery systems containing GSIs and surface modified with DR-5 and DLL4 monoclonal antibodies (mAb) to effectivity target and treat TNBC. The delivery system is designed to deliver the drug cargo precisely to TNBCs through its DR-5 receptors and hence expected to reduce the off-target side effects of GSIs. Further, DLL4 mAb and GSIs are expected to act synergistically to block the Notch signal mediated BCSCs proliferation, differentiation, and metastasis.

In this paper, a 16-phases 20 MHz to 110MHz low jitter delay locked loop, DLL, is proposed in a 0.35 mm CMOS process. A sensitive open loop phase detector, PD, is introduced based on a novel idea to simply detect small phase differences between reference clock and generated delayed signals. High sensitivity, besides the simplicity reduces the dead zone of PD and gives a better jitter on output generated clock signals, consequently. A new strategy of common mode setting is utilized on differential delay elements which no longer introduce extra parasitics on output nodes and brings the duty cycle of generated clock signals near to 50 percent. Also, small amplitude differential clock is carefully transferred inside the circuit to considerably suppress the noise effect of supply voltage. Post-Layout simulation results confirm the RMS jitter of less than 6.7 ps at 20 MHz and 2 ps at 100 MHz input clock frequency when the 3.3 Volts supply voltage is subject to 75 mVolts peak-to-peak noise disturbances. Total power consumption reaches from 7.5 mW to 16.5mW when the operating frequency increases from 20MHz to 100MHz. The proposed low-jitter DLL can be implemented in small active area, around 380 mm × 210 mm including the clock generation circuit, which is proper to be repeatedly used inside the chip.

In this paper a new architecture for delay locked loops is proposed. Static phase offset and reset path delay are the most important problems in phase-frequency detectors (PFD). The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of phase difference between input and output of the DLL. Near locking, an XOR gate is used to act as a PFD which makes the DLL locks with less jitter. Also, the reset path time and glitch are decreased by using the XOR gate. The proposed architecture has been designed in TSMC 0.18um CMOS Technology. The simulation results support the theoretical design aspects.

In this paper, a new scheme named "modified coherent DiLL" is proposed for tracking direction of arrival of signals in direct-sequence code-division multiple-access systems. This scheme has a similar concept to the delay lock loop that is used for time synchronizing in CDMA systems. The proposed scheme is able to track the DOA of the arriving signals iteratively. The properties of the proposed scheme such as computational and mean square error are compared to the coherent and noncoherent DiLL. The new scheme consists of 2NK+O(K) computations, where Nand K are the number of antenna sensors and signal sources, respectively. The computation is two-folds and approximately the same Mean Square error as coherent DiLL scheme, while it does not require estimating. Data and phase of the received carrier signal. In addition, the computation of this method is approximately equal, and mean square error is half of the noncoherent DiLL.

Objectives: To investigate the relationship of the core power and endurance with variables of athletic performance such as T test, medicine ball throw test, vertical jump test and 40 yard dash test in random intermittent dynamic type sports (RIDS). Methods: 58 male collegiate athletes involved in RIDS with mean age of 19. 41  1. 19 years, height of 172  6. 62 cm, weight of 67. 41  8. 80 kg and BMI of 22. 56  2. 00 participated in this correlation study. The subjects were tested for core power, core endurance and performance variables. The core endurance was measured by McGill protocol and double leg lowering test (DLL) and the core power was measured by 60 seconds maximal sit-up test. Results: McGill protocol was positively correlated with medicine ball throw test (r = 0. 688) and vertical jump test (r = 0. 463). A strong negative correlation of McGill was identified with 40 yard dash test (r =-0. 525) and T test (r =-0. 687). At the same time DLL was positively correlated with 40 yard dash test (r = 0. 374) and T test (r = 0. 524). Only medicine ball throw test related significantly with the tests of core power. Conclusions: McGill test and DLL more significantly correlates with the performance variables such as medicine ball throw test, vertical jump test, 40 yard dash test and T test when compared with the core power measures of 60 seconds maximal sit-up test. The current study results also show that core muscle endurance is necessary for optimal performance and should not be neglected.