Today more than ever, we need high-speed circuits with low occupancy and low power as an alternative to CMOS circuits. Therefore, we proposed a new path to build nanoscale circuits such as Quantum-dot Cellular Automata (QCA). This technology is always prone to failure due to its very small size. Therefore, designers always try to design fault-tolerant GATEs and provide methods to increase the reliability of QCA. By adding redundant cells, the possibility of some defects such as cell omission and cell addition is somewhat reduced. However, in the face of defects such as stuck-at 0/1 faults, Clock fault and bridging fault. We can greatly increase the fault tolerance by appropriate placement and using fault tolerant GATEs with a suitable structure. In this paper, we design the XOR/XNOR GATE with the approach of preventing stuck-at 0/1 fault, clock fault, and bridging fault using the first NNI GATE tolerating cell addition fault.

This work investiGATEs the channel thickness dependency of high-k GATE dielectric-based complementary metal-oxide-semiconductor (CMOS) inverter circuit built using a conventional double-GATE metal GATE oxide semiconductor field-effect transistor (DG-MOSFET). It is espied that the use of high-k dielectric as a GATE oxide in n/p DG-MOSFET based CMOS inverter results in a high noise margin as well as gain. It is also found that delay performance of the inverter circuit also gets upgraded slightly by using high-k GATE dielectric materials. Further, it is observed that the scaling down of channel thickness (TSi) improves the noise margin (NM), and gain (A) at the cost of propagation delay (Pd). Moreover, it is also observed that the changes in noise margin (Δ, NM = NM(K=40) –,NM(K=3. 9)), propagation delay (Δ, Pd = Pd (K=40) –,Pd (K=3. 9)), and gain (Δ, A = A(K=40) –,A(K=3. 9)) gets hinder at lower TSi. Therefore, it is apposite to look at lower channel thickness (~6 nm) while designing high-k GATE dielectric-based DG-MOSFET for CMOS inverter cell.

Two-dimensional analytical modelling of Dual Material GATE Tunnel Field Effect Transistor with change in variation of GATE oxide thickness (DMG-UOX-TFET) is proposed in this work. This proposed device employs dielectric materials such as hafnium oxide and silicon dioxide, with distinct oxide thicknesses. This device was invented using a technology-aided computer design tool in 10 nm (0.01 µm) technology. This work investiGATEs the impact of GATE oxide thickness on the electrical characteristics of the proposed device, with a particular focus on drain current variation. The extensive simulations and key performance parameters of the proposed device were analyzed regarding GATE oxide thickness. The various GATE oxide thicknesses and their effects on the device subthreshold slope, On- current, Off- current, and on-off-current ratio were analyzed. The proposed device incorporates n-type operations within the GATE overlap region, effectively mitigating the corner effect and the detrimental band-to-band tunneling that can degrade the on/off ratio. Through careful optimization of the doping concentration in the GATE overlap region, achieved a remarkable ∼4.8 time enhancement in the on-current, while simultaneously reducing the average subthreshold swing from 91.3 mV/dec to 52.8 mV/dec.

This paper presents a one-dimensional analytical model for calculating GATE capacitance in GATE-All-Around Carbon Nanotube Field Effect Transistor (GAA-CNFET) using electrostatic approach. The proposed model is inspired by the fact that quantum capacitance appears for the Carbon Nanotube (CNT) which has a low density of states. The GATE capacitance is a series combination of dielectric capacitance and quantum capacitance. The model so obtained depends on the density of states (DOS), surface potential of CNT, GATE voltage and diameter of CNT. The quantum capacitance obtained using developed analytical model is 2.84 pF/cm for (19, 0) CNT, which is very close to the reported value 2.54 pF/cm. While, the GATE capacitance comes out to be 24.3×10-2 pF/cm. Further, the effects of dielectric thickness and diameter of CNT on the GATE capacitance are also analysed. It was found that as we reduce the thickness of dielectric layer, the GATE capacitance increases very marginally which provides better GATE control upon the channel. The close match between the calculated and simulated results confirms the validity of the proposed model.