Nowadays, the use of hardware/software codesign has grown dramatically in the design of embedded systems since it can improve the processing power, system efficiency, and the total cost of production. In this method, some parts of the system are implemented in hardware and the other parts are implemented in software in order to satisfy the system constraints, including power consumption, area and processing time. This paper proposes a parallel architecture for motion estimation in HEVC encoder. In the proposed method, the motion estimation part of the encoder, which has a high computational complexity, is implemented in hardware, and the computational complexity of this part is improved using parallel processing. The hardware implementation of motion estimation part is much less complex than the adopted HM reference software, making it more suitable for embedded systems. Experimental results show a significant improvement over software implementation.

Intra coding in High efficiency video coding (HEVC) can significantly improve the compression efficiency using 35 intra-prediction modes for 2N´2N (N is an integer number ranging from six to two) luma blocks. To find the luma block with the minimum rate-distortion, it must perform 11932 different rate-distortion cost calculations. Although this approach improves coding efficiency compared to the previous standards such as H.264/AVC, but computational complexity is increased significantly. In this paper, an intra-prediction technique has been described to improve the performance of the HEVC standard by minimizing its computational complexity. The proposed algorithm called prediction unit size decision (PUSD) was introduced to decrease evaluation of block sizes. The simulation results show that the time complexity is decreased by ~36% while the bit-rate is increased by 1.1 kbps, and PSNR is decreased by 0.6 db. Accordingly, the proposed algorithms have negligible effect on the video quality with great saving in the time complexity.

High Efficiency Video Coding (HEVC) is considered the last standard for video compression with about 50% additional compression compared to the previous standard i. e. H264/AVC, while maintaining image quality. The significant increase in performance of this standard has been achieved with high computational complexity. In this standard, the intra prediction unit is one of the parts that although it greatly improves performance, it significantly increases its computational complexity due to the increase in the number of prediction modes. In this paper, a method has been proposed to reduce the number of intra prediction modes in HEVC by which the computational complexity of compression at this stage can be reduced as much as possible. The proposed method determines the predominant mode of 4 × 4 blocks, and the details in each larger block, and accordingly, by applying the appropriate filters and selecting the most likely mode, the number of candidate modes to select the best mode is reduced. The simulation results showed that on average the proposed method can reduce the compression time by 45% while increasing the bit rate by 0. 69%.

Videos directly captured from a computer or smartphone screen have certain characteristics that differentiate them from camera-captured (CC) ones. These videos are called screen content (SC) videos whose specific encoder has been introduced as a new extension of the HEVC standard called screen content coding (SCC). Most screen content applications are real-time with low delay requiring an accurate rate control. The difference in the characteristics and use of special coding tools such as palette mode, intra block copy, and adaptive color transform in this standard, have affected the mechanism of bit rate generation and control. This paper presents methods and criteria to evaluate the controllability of the bit rate of SC videos and compare it with that of CC counterparts. Furthermore, the requirements of SC video rate control are studied. The experimental results indicate that the bit rate of SC videos is much less controllable than the conventional ones so that the conventional rate-distortion models and bit rate control algorithms are not effective in coding the SC videos.

High Efficiency Video Coding (HEVC) is one of the latest coding standards targeting high-resolution video contents. Due to the high complexity of the existing hardware implementation, this paper presents the low-cost and efficient DCT architectures for HEVC, which are able to perform DCT operation of multiple transform sizes in a single unified architecture. Our objective is to reuse the hardware resources in a DCT architectures using configurable constant multipliers as well as reducing the hardware cost and trading off between hardware complexity and efficiency. We propose three different shift-and-add units with different hardware cost and throughput. The main advantage of the proposed architectures over the existing architectures is a lower hardware and it can also perform DCT transform of different transform units which is available in HEVC standard. The experimental results over 90-nm technology show that the proposed 2D-DCT architecture #1 archives the lowest hardware cost amongst the rest of the architectures with around 57% reduction in gate count, on average. The unfolded 2D-DCT architectures #2 and #3 offer the moderate reduction in gate count around 47%, on average, with a moderate throughput. Apart from architectures #1, #2, and #3, we also develop a reusable architecture by adding an extra (𝑁 /2)-point DCT alongside the main DCT.