High dynamic range and adjustability of gain are the main requirements in low-voltage audio-frequency transconductors. There are several methods for designing a low voltage transconductor however, most of them have a fixed Transconductance over their input range. In this paper a low distortion ohmic transconductor with adjustable gain has been designed. The circuit can operate from 3 V single power supply and has a very low distortion by choosing normal dimension for W/L of feedback transistors. To consider stray capacitances of the circuit we also perform L-Edit extraction. Then the final circuit has been carried out with 0.8.um CMOS Technology. Simulation has resulted a very low distortion as small as 0.2% for a 1.8Vpp sinusoidal input.

The operational Transconductance amplifier-capacitor (OTA-C) filter is one of the best structures for implementing continuous-time filters. It is particularly important to design a universal OTA-C filter capable of generating the desired filter response via a single structure, thus reducing the filter circuit power consumption as well as noise and the occupied space on the electronic chip. In this study, an inverter-based universal OTA-C filter with very low power consumption and acceptable noise was designed with applications in bioelectric and biomedical equipment for recording biomedical signals. The very low power consumption of the proposed filter was achieved through introducing bias in subthreshold MOSFET transistors. The proposed filter is also capable of simultaneously receiving favorable low-, band-, and high-pass filter responses. The performance of the proposed filter was simulated and analyzed via HSPICE software (level 49) and 180 nm complementary metal-oxide-semiconductor technology. The rate of power consumption and noise obtained from simulations are 7.1 nW and 10.18 nA, respectively, so this filter has reduced noise as well as power consumption. The proposed universal OTA-C filter was designed based on the minimum number of Transconductance blocks and an inverter circuit by three Transconductance blocks (OTA).

With advancement of integrated circuit technology and aggressive scaling into nanometer regime, statistical variability in device electrical characteristics caused by discreteness of charge and fabrication process variations has significantly increased. These variations in turn result in fluctuations in output characteristics of important analog building blocks and in particular, amplifiers. In this paper, with the aid of Monte-Carlo simulations for a Transconductance amplifier and using 1000 different compact models of MOSFET transistors in 35nm technology node, statistical variations of important circuit parameters are investigated and analyzed based on their statistical distributions. Moreover, statistical correlations between circuit parameters are extracted. Analysis of statistical variations for circuit parameters and their correlations has a direct impact on reduction of cost and time of a design and thus, is of great amount of significance.

This paper is based on analysis of a common source-common gate low noise Transconductance amplifier (CS-CG LNTA). Conventional noise analyses equations are modified by considering to the low output impedance of the sub-micron transistors and also, parasitic gate-source capacitance. The calculated equations are more accurate than calculated equations in other works. Also, analyses show that the noise of the tail transistor, which is utilized to bias the common gate transistor, will limit noise canceling advantages. So, the common gate transistor is biased by a resistor. That leads to a significant improvement in noise figure. By utilizing a Taylor series expression, a closed-form equation is obtained to calculate IIA3 for the first time. Finally, based on the calculated equation a design procedure is proposed.

High gain Balun-low-noise-amplifier (LNA) is proposed for tuner of digital televisions (DTVs). The proposed Balun-LNA is based on CS-CG (common-source-common-gate) structure. To improve the isolasion and frequency response, Balun-LNA has cascode transistors before load resistors. Balun-LNA uses current-bleeding circuit to increasie Transconductance of CS transistor, so that current-bleeding transistor has Transconductance of N-1 times larger than Transconductance of cascode transistor. Thereby, Transconductance and current of CS transistor are increased N times, as N-1 times of current pass to current-bleeding transistor. Therefore current of CG and CS stages stay identical. Also, Balun-LNA employs a positive feedback to satisfy input impedance matching and CG transistor has higher Transconductance. By increasing Transconductance of CS and CG transistors, the proposed Balun-LNA achieves to high voltage gain. Accordingly, CG and CS tansistors have symmetrical currents and loads at the differential output of the proposed Balun-LNA. Symmetrical loads cause the balanced differential outputs. This proposed Balun-LNA is designed in 90-nm CMOS technology and covers the frequency range of 40 MHz to 1GHz. This Balun-LNA achieves the voltage gain of 22.6 dB, S11 of less than -10 dB and the Minimum NF of 5 dB. This Balun-LNA operates at the nominal supply voltage of 2.2v.

A dual-halo dual-dielectric triple-material cylindrical-gate-all-around/surrounding gate (DH-DD-TMCGAA/ SG) MOSFET has been proposed and an analytical model for the Transconductance-to-drain current ratio (TDCR) has been developed. It is verified that incorporation of dual-halo with dualdielectric and triple-material results in enhancing the device performance in terms of improved TDCR. The effect on TDCR is analyzed for variations in device parameters like oxide thickness, silicon thickness, channel doping concentration, channel length and drain bias. The results show that larger value of gm/Id can be obtained in proposed device in comparison to other existing triple material structures which makes it suitable for micropower applications. The analytical results of the developed gm/Id model strongly agrees with the simulated results obtained from TCAD Silvaco.

Background and Objectives: In wireless communications, receivers play an essential role. Among receiver architectures, the direct-conversion receiver (DCR) architecture has been selected due to its high level of integration and low cost. However, it suffers from DC offset due to self-mixing, I/Q imbalance, and flicker noise.Methods: This paper presents a new LNA-mixer with variable conversion gain (VG-LM) for wireless local area network (WLAN) applications. A low noise Transconductance amplifier (LNTA) is used as the Transconductance stage in the Gilbert cell mixer. The wide variable conversion gain range is achieved by the change in LNTA’s Transconductance and Transconductance of the mixer switching transistors.Results: The proposed LNA-mixer is designed and simulated using 0.18µm CMOS technology in Cadence Spectre RF. The post-layout simulations exhibit the proposed circuit operates at 2.4 GHz with a bandwidth of 10 MHz. In addition, the conversion gain is changed from -3.9 dB to 23.9 dB with the variation of the controlled DC voltage from 0.5 to 1.8. At the high gain, the double-sideband noise figure (DSB-NF) is less than 3.7 dB, and its third-order intermodulation point (IIP3) is -9 dBm. The power consumption is 22 mW from the supply voltage of 1.8 V. The circuit occupies 743 µm×775 µm of core chip area.Conclusion: Using the proposed circuit, the RF front end receiver does not need the low noise amplifier (LNA) and variable gain amplifier (VGA).

In Junctionless transistors, the source-channel-drain doping is of the same type and level, hence, the process of making Junctionless transistors is easier than inverting mode transistor. Despite this benefit, reducing the Transconductance of Junctionless transistors due to reduced carrier velocity makes the operation of this type of transistor difficult for analog, radio frequency and high frequency noise usages. An effective method that increases the trans-conductance of Junctionless transistors without reducing efficiency is using a heterogeneous structure in the channel. In the present article, using Si and Si1-xGex materials in the channel is proposed and modeled so as to enhance the Transconductance of Junctionless transistor. The special structure of the proposed transistor, called JL-Si / Si1-xGex, eliminates the intervalley scattering between valleys of ∆2 and ∆4. This increases the velocity of the electron and consequently enhances the Transconductance. The outcomes of the modelling of the proposed JL-Si / Si1-xGex heterostructure transistor indicate the maximum Transconductance of 2.5 mS / um, which increases 50% compared to similar silicon transistor. Moreover, calculations which are extracted from modelling demonstrate that the proposed JL-Si / Si1-xGex transistor has a unity gain cutoff frequency of 750 GHz, minimum noise figure of 65.0 dB, and an available gain of 28.5 dB. The parameters of cut-off frequency, minimum noise figure and available gain of the proposed JL-Si / Si1-xGex transistor have been improved by 34%, 62.5% and 53%, respectively, compared to the JL-Si transistor with similar dimensions. The proposed device can be suitable candidate for RFIC applications.

The devices with additional gates like Fin Field effect transistor (FinFET) provide higher control on subthreshold parameters and are favorable for Ultra large-scale integration. Also, these structures provide high control on current through the channel and with minimum leakage. In this paper we designed a FinFET with high-K gate dielectric material i. e Hafnium oxide as gate oxide. A comparison of similar sized transistor with Air and Silicon dioxide as gate material is performed. The comparison is mainly in terms of performance parameters like Transconductance, subthreshold slope, and drain current characteristics. There is an increase in ON current on using a high-K dielectric material and subsequently an improvement in other parameters like subthreshold slope, Transconductance and intrinsic gain.

In this paper, the impact of the undoped and recessed gate structure on the performance of the silicon carbide metal semiconductor field effect transistor is presented. The importance of the silicon carbide metal semiconductor field effect transistor analyzed using technology computer aided design simulations in 10 nanometer technology. The proposed undoped gate structure has minimized ionized impurity scattering, leading to increased electron mobility and improved carrier concentration. Performance metrics such as drain current, Transconductance, subthreshold slope, and cutoff frequency were evaluated and compared with conventional silicon carbide metal semiconductor field effect transistor structures. The proposed device exhibits superior current driving capabilities, enhanced Transconductance, and reduced leakage currents, leading to improved power efficiency. Moreover, the recessed gate structure contributes to a significant reduction in short-channel effects, making the device more suitable for high frequency applications. The simulation parameters were calculated and compared with conventional structure with the length of the source and drain in 10 nanometer node. Therefore the drain current of this proposed device has been improved by 68%.