This paper proposes the efficient VLSI architecture of camera distortion correction, based on a Neural Camera Distortion Model (NCDM). Conventional imaging methods use over two kinds of models to correct the camera and lens distortions, but the NCDM uses a single model to immediately correct the geometry distortion and unsymmetrical manufacturing errors. The NCDM, with four neurons, performs a wide-angle distortion correction. The results show that the maximal corrected error in a whole image is less than 1.1705 pixels, and the MSE approaches 0.1743 between corrected and ideal results. The distortion correction by NCDM is 429more accurate than the conventional approach. The chip size of NCDM is 1: 51×1: 51 mm2 and contains 126 K gates using the TSMC 90 nm CMOS technology process. Working at 240 Mhz, this architecture can correct 30 frames and a Full-HD resolution video per second. Results show that the maximal corrected error in a whole image is less than 1.4 pixels, and the mean square error approaches 0.0376 between corrected and ideal results.

Image data require huge amounts of disk space and large bandwidths for transmission. Hence, image compression is necessary to reduce the amount of data required to represent a digital image. Therefore an efficient technique for image compression is highly pushed to demand. Although, lots of compression techniques are available, but the technique which is faster, memory efficient and simple, surely hits the user requirements. In this paper, the image compression, need of compression, its principles, how image data can be compressed, and the image compression techniques are reviewed and discussed. Also, wavelet-based image compression algorithm using Discrete Wavelet Transform (DWT) based on B-spline factorization technique is discussed in detail. Based on the review, some general ideas to choose the best compression algorithm for an image are recommended. Finally, applications and future scopes of image compression techniques are discussed considering its development on FPGA systems.

Viterbi decoder is used for decoding data encoded using Convolution Forward Error Correction codes or data that suffers from inter-symbol interference. They occur in a large proportion of digital transmission. Viterbi decoders employed in digital wireless communications are complex and dissipate large power. The proposed method focuses on gate diffusion input (GDI) which is a low power technique of digital circuit design. Dynamic component of power is reduced in GDI technique as source of PMOS is not permanently connected to Vdd. It also reduces the latency of the circuit. The Viterbi decoder is implemented using GDI cell with 0.25 mm and 90 nm technology with 2.5 V Vdd. Frequency is varied from 15 MHz to 25 MHz. The outputs of the convolutional encoder designed for the constraint lengths K 4, 5, 6, 7 and rate are fed to the designed Viterbi decoder. The comparison results showed 29% reduction in power consumption and 66% reduction in area by using GDI circuit than the CMOS circuit.

An SPICE compatible model for multiple coupled nonuniform lossless transmission lines (TLs) is presented. The method of the modeling is based on the steplines approximation of the nonuniform TLs and quasi-TEM assumptions. Using steplines approximation the system of coupled nonuniform TLs is subdivided into arbitrary large number of coupled uniform lines (steplines) with different characteristics. Then using modal decomposition method the system of coupled partial differential equations for each step is decomposed to a number of uncoupled ordinary wave equations describing uncoupled uniform TLs in each step. To satisfy the boundary conditions at the discontinuities a new model is developed. Therefore each step of the system can be modeled in SPICE using a set of ideal delay lines representing uncoupled TLs and some linear-dependent voltage and current sources. Finally some examples are given to show the validity and usefulness of the model.

The process of placement, which involves determining the spatial coordinates of numerous standard cells and macros, is a critical and labor-intensive stage in contemporary Very Large-Scale Integration (VLSI) physical design. The placement of components in a circuit has long been challenging due to the increasing complexity of structures and the continuous advancements in VLSI manufacturing techniques. This research introduces a Reinforcement Learning (RL) strategy known as the Reinforcement Learning Parameter Optimization Model (RLPOM) and a Graph Neural Network (GNN) to formulate the parameter optimization problem as a RL task. The agent is trained exclusively using RL through a self-search approach. The selection of the RL algorithm is motivated by the need to address the challenges posed by data sparsity and latency in placement runs. The mean outcomes of the proposed RLPOM across all performance measures are as follows: The measured parameters for the system under study include wire length (13. 71 um), congestion (4. 5%), area utilization (82. 4%), run time (26. 68 sec), power consumption (15. 57 W). This approach leverages the natural advantages of GNN and RL to achieve superior global placement, which is unique to the best of our knowledge.