Reversible logic has been emerged as a promising computing paradigm to design low power circuits in recent years. The synthesis of reversible circuits is very different from that of non-reversible circuits. Many researchers are studying methods for synthesizing reversible combinational logic. Some automated reversible logic synthesis methods use optimization algorithms Optimization algorithms are used in some automated reversible logic synthesis techniques. In these methods, the process of finding a circuit for a given function is a very time-consuming task, so it’, s better to design a processor which speeds up the process of synthesis. Application Specific Instruction Set Processors (ASIP) can benefit the advantages of both custom ASIC chips and general DSP chips. In this paper, a new architecture for automatic reversible logic synthesis based on an Application Specific Instruction Set Processors is presented. The essential purpose of the design was to provide the programmability with the Specific necessary Instructions for automated synthesis reversible. Our proposed processor that we referred to as ARASP is a 16-bit processor with a total of 47 Instructions, which some Specific Instruction has been Set for automated synthesis reversible circuits. ARASP is specialized for automated synthesis of reversible circuits using Genetic optimization algorithms. All major components of the design are comprehensively discussed within the processor core. The Set of Instructions is provided in the Register Transform Language completely. Afterward, the VHDL code is used to test the proposed architecture.

Reconfigurable Instruction Set Processors allow customization for an Application domain by extending the core Instruction Set architecture.Extracting appropriate custom Instructions is an important phase for implementing an Application on a reconfigurable Instruction Set processor. A custom Instruction (CI) is usually extracted from critical portions of Applications and implemented on a reconfigurable functional unit. In this paper, our proposed RFU architecture for a reconfigurable Instruction Set processor is introduced. As the main contribution of this work, an integrated framework of temporal partitioning and mapping is introduced that partitions and maps CIs on the RFU. Temporal partitioning iterates and modifies partitions incrementally to generate CIs. The proposed framework improves the timing performance particularly for the Applications comprising a considerable amount of CIs that could not be implemented on the RFU due to architectural limitations. Furthermore, exploiting similarity detection and merging as two complementary techniques for the integrated framework brings about reduction in the configuration memory size.

The increasing diversity in packet-processing Applications together with the rapid increase in channel bandwidth has brought about greater complexity in communication protocols. Also influenced by these factors is the computational load for packet-processing engines, demanding high performance microprocessor designs as an indispensable solution. This paper reports on extensive simulation experiments carried out for exploring the performance of Instruction-level parallel Very Long Instruction Word (VLIW) Processors executing packet processing Applications. On the grounds of the experimental results, a design space exploration has been used to derive an efficient Application-Specific VLIW processor architecture based on the VEX Instruction Set architecture. The VEX simulator toolSet has been used for design space exploration, and a number of networking Applications have been chosen to serve in guiding the architectural exploration.The optimization measures achieve up to 60% improvement in performance for the most representative packet-processing Applications.

Prolonged exposure to gases in enclosed spaces, can cause health problems that may not be easily eliminated, Several methods have been developed to determine the concentration of aromatic hydrocarbons. But these methods have certain limitations, which complicate the titration. Regression-based methods can be used using the software and applying numerical methods to the data obtained to determine the concentration of gases. The main idea of this paper: is to keep up with the ideal balance, and limit the deficiency of necessary to obtained from spectroscopic data, and the effect of mutilations presented by different noise decreases and autofluorescence background elimination algorithms was determined from the comparison data. And these changes ratios were in remove background fluorescence(benzene, toluene, xylene), for the (PolyFit) method they were 3% and 5% and 2%, and for the (ModPoly) method they were 1% and 2% and 2%, and for the gas processor method, they were 2% and 5% and 2 %, respectively. So it was noticed it has been noticed here that the proposed method (GasesProcessors) is better in terms of filter performance and autofluorescence background removal compared to other methods.