We have developed the effective algorithm for detecting digital binary PHASE-shift keyed signals. This algorithm requires a small number of arithmetic operations over the signal period. It can be relat ively easy implemented based on the modern programmable logic devices. It also provides high interference immunity by identifying signal presence when signal-to-noise ratio is much less that its working value in the receiving path. The introduced DETECTOR has int rinsic frequency selectivity and allows us to form the est imate of the noise level to realize the adaptive determination of decision threshold. In order to get confirmation of the DETECTOR operability and performance, we suggest the expressions for false alarm and missing probabilities. In addit ion, we have examine, both theoretically and experimentally, the influence of the DETECTOR parameters on its characterist ics.

This work introduces a new structure of Zero Crossing Digital PHASE Locked Loop with Arc Sine block (ASZCDPLL) to linearize the PHASE difference detection, and enhance the loop performance. The new loop has faster acquisition, less steady state PHASE error, and wider locking range as compared to the conventional ZCDPLL. The locking range improvement and faster acquisition have been confirmed through simulation. The loop has been implemented and tested in real time using Texas Instruments TMS320C6416 DSP development kit.

In this paper a new PHASE-frequency DETECTOR is proposed using transmission gates which can detect PHASE difference less than 500ps. In other word, the proposed PHASE-frequency DETECTOR (PFD) can work in frequencies higher than 1. 7 GHz, whereas a conventional PFD operates at frequencies less than 1. 1 GHz. This new architecture is designed in TSMC 0. 13um CMOS Technology. Also, the proposed PFD achieves a capture range approximately twice that of conventional PFDs. The simulation results support the theoretical predictions. To validate correct performance of this novel PFD, it is then used in a conventional delay locked loop structure.

The electronic industry has grown vastly in recent years, and researchers are trying to minimize circuits delay, occupied area and power consumption as much as possible. In this regard, many technologies have been introduced. Quantum Cellular Automata (QCA) is one of the schemes to design nano-scale digital electronic circuits. This technology has high speed and low power consumption, and occupies very little area. PHASE-locked loops (PLLs) and delay-locked loops (DLLs) are blocks that are commonly used in telecommunication applications. One of the most important parts in DLL and PLL is the PHASE-frequency DETECTOR. Therefore, the design of this circuit in QCA technology is of great importance. In this paper, two new PHASE-frequency DETECTORs sensitive to falling and rising edge have been introduced in QCA technology. Both of the designs are composed of 104 cells; occupy only 0. 13 μ m2 of an area and 1. 5 QCA clock cycles latency. The designs are in one layer and all the inputs and outputs are available to be used by another circuit.

In this paper a new architecture for delay locked loops is proposed. Static PHASE offset and reset path delay are the most important problems in PHASE-frequency DETECTORs (PFD). The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of PHASE difference between input and output of the DLL. Near locking, an XOR gate is used to act as a PFD which makes the DLL locks with less jitter. Also, the reset path time and glitch are decreased by using the XOR gate. The proposed architecture has been designed in TSMC 0.18um CMOS Technology. The simulation results support the theoretical design aspects.