In today's technological environment, designing the Static Random Access Memory (SRAM) is most vital and critical memory devices. In this manuscript, two kinds of 5TSRAM are designed using different CNTFET such as Dual-ChiralityGate all around (GAA) CNTFET and Ballistic wrap gate CNTFET based 5T SRAM cell designs for enhancing the read/write assist process. Here, the proposed Dual-ChiralityGAA-CNTFET based 5T-SRAM has two cross-coupled inverters using one access transistor that is connected to the bit line (BL) and word line (WL) through minimum supply voltage. Instead of cross-coupled inverter circuit, the BWG-CNTFET based 5T-SRAM cell is intended for achieving less power and improved read/write assist process. Also, one transistor is executed as low-threshold (LVT) device in the proposed BWG-CNTFET based 5T-SRAM. Thus, proposed two kinds of 5T SRAM cells increases the read/write assist operation and reduce the leakage current/ power. The simulation of the proposed two kinds of 5T SRAM cell is done by HSPICE simulation tool and the performance metrics are calculated. Therefore, the proposed Dual-ChiralityGAA-CNTFET based 5T-SRAM cell design has attained 11.31%, 51.47% lower read delay, 44.44%, 26.33% lower write delay, 36.12%, 45.28% lower read power, 34.5% , 22.41% lower write power, 37.4%, 15.3% higher read SNM and 35.8%, 12.09% higher write SNM than Double gate carbon nanotube field effect transistors (DG CNTFET) and state-of-art method respectively. Similarly, the proposed BWG-CNTFET 5T SRAM cell design has attained 45.53%, 38.77% lower write delay, 56.67%, 45.64% lower read delay, 58.4%, 56.75% lower read power, 49.66%, 28.56% lower write power, 35.32%, 12.7% higher read SNM and 45.8%, 15.6% higher write SNM than Reduced Power with Enhanced Speed (RPES) approach and state-of-art method respectively.

The overall performance of any integrated circuit is defined by its proper memory design, as it is a mandatory and major block which requires more area and power. The prime interest of this article is to design a memory structure which is tolerant to variations in CNFET (Carbon nanotube field effect transistor) parameters like pitch, diameter and number of CNT tubes, and also offer low power and high speed of operation. In this context, CNFET based stacked SRAM (Static random access memory) design is proposed to attain the above mentioned criteria. Concept of stack effect is utilized in the cross coupled inverter section of the memory structure to attain low power. The power, speed and energy analysis for the proposed structure is done, and compared with the conventional structures to justify the proposed memory cell performance. HSPICE simulation results has confirmed that the proposed structure offers about 34%, 54% and 95% power saving in hold mode, read mode and write mode respectively. In speed and energy point of view it provides about 97% read delay, 92% write delay and 98% energy savings than the conventional memory structures. These results make it clear that the proposed SRAM is suitable for the 5G networks where circuit speed, power and energy consumption are the major concern.

Three new SRAM cells are proposed in this paper. Increasing area overhead is the major concern in SRAM design.One of the new structures is included four transistors instead of six transistors as it is used in conventional 6T-SRAM cell for very high density embedded SRAM applications. The structure of proposed SRAM employs one word-line and one bit-line during Read/Write operation. The new SRAM cell has smaller size, leakage current and power dissipation in contrast of a conventional six transistor SRAMs. A proposed 4T-SRAM cell has been simulated for 256 cells per bit-line and 128 columns cell for supply voltage of 1.2V. Furthermore, two other new structures are included 10 and 11 transistors. These new structures have been separate read and write process by changing in the structure of conventional 6T SRAM to achieve high Static Noise Margin (SNM). Using 10T and 11T SRAM cells lead to apply 512 cells per bit-line by reducing leakage current technique, while the cell is unavailable.128 columns cell array has been built to measure the operation of SRAM cell. To have low power dissipation, the supply voltage for 10T and 11T are chosen 0.32V and 0.27V, respectively. Proposed SRAM uses one read bit-line during read operation. Simulation results have been confirmed by HSPICE in 0.13um process.

This paper presents analysis of the Static Noise Margin (SNM), power dissipation, access time and dynamic noise margin of a novel low power proposed 8T Static Random Access Memory (SRAM) cell for read operations. In the proposed structure, two voltage sources are used, one is connected with the bit line and the other is connected with the bitbar line in order to reduce the voltage swing at the output nodes of the bit and the bit bar lines. Simulation results for the read static noise margin, read power dissipation, read access time and dynamic noise margin have been compared to those of other SRAM cells, reported in dierent literatures. It is shown that the proposed SRAM cell has better static noise margin and dissipates less power in comparison to other SRAM cells. Analog and schematic simulations have been done in a 45 nm environment with the help of Microwind 3.1, using the BSimM4 model.