THE CSI JOURNAL ON COMPUTER SCIENCE AND ENGINEERING
Year:2018 | Volume:15 | Issue:2|Papers Count:6

Executing all steps of an algorithm that faces with massive input data may take a long time. A progressive algorithm solves the problem step by step, and produces a partial solution in each step which approximates the final solution. Therefore, the user can decide to stop the algorithm or continue to get better solutions. In this paper, we consider the problem of sorting a set of N real numbers, and design a progressive algorithm with 𝑂 (log𝑀 /𝐵 𝑁 /𝐵 ) steps that takes 𝑂 (𝑁 /𝐵 ) I/O operations in each step in the external memory model. The upper bound for the error of the partial solution in step r is 𝑂 (𝑁 (𝑀 /𝐵 )𝑟 /2).

Continuous changes in organizational requirements, including the architecturally significant ones, have drawn researchers' attentions to the importance of architecture evolution process. Considering the widespread effect of structural design decisions, the consistency with previously designed architectural structures should thus be continuously preserved throughout the evolution process. Evolving Enterprise Architecture (EA) and Software Architecture (SA), as a kind of architectural structure, is thus important. One of the approaches for managing this process is managing the evolution process knowledge. The knowledge that has been used for designing the architecture is as valuable as the designed architecture itself because the architecture would be destroyed if it is updated without considering the knowledge that was used (or created) during the design process. On the other hand, one of the reasons for which updating the architecture is important is the need for aligning SA and EA. Although the idea of using Knowledge Management (KM) process for evolving architecture has somehow been addressed, researchers have sporadically studied the applicability of using KM techniques for addressing the alignment issues. In this research, a framework is proposed for aligning the SA and EA based on KM process. Architectural designers can use this framework for aligning the architectures, and researchers can use it for proposing new alignment methods.

Nowadays, the use of hardware/software codesign has grown dramatically in the design of embedded systems since it can improve the processing power, system efficiency, and the total cost of production. In this method, some parts of the system are implemented in hardware and the other parts are implemented in software in order to satisfy the system constraints, including power consumption, area and processing time. This paper proposes a parallel architecture for motion estimation in HEVC encoder. In the proposed method, the motion estimation part of the encoder, which has a high computational complexity, is implemented in hardware, and the computational complexity of this part is improved using parallel processing. The hardware implementation of motion estimation part is much less complex than the adopted HM reference software, making it more suitable for embedded systems. Experimental results show a significant improvement over software implementation.

Various methods have been proposed for constructing and optimizing fuzzy inference systems. This paper first proposes a new method to cre-ate zero-order Sugeno fuzzy inference systems using the Shuffled Frog Leaping Algorithm (SFLA). As the second contribution, the paper introduces four improvements over SFLA. The resulting version of SFLA, called ISFLA (Improved SFLA), is also applied to create zero-order Sugeno fuzzy inference systems. We conducted experiments to assess ISFLA and compare it with the original SFLA and three well-known evolutionary algorithms over five standard classification data sets from the UCI machine learning repository. The experimental results show that ISFLA creates fuzzy systems more efficiently than the standard SFLA and some other evolutionary algorithms, i. e., GA, ACO and PSO. Moreover, with respect to the accuracy and the convergence speed criteria, ISFLA and PSO outperform other evolutionary algorithms, while their performance is comparable to each other.

VLSI technology scaling has resulted in the integration of a larger number of cores in a single chip in successive technology nodes, offering a great potential to realize task-level redundancy for reliability enhancement in safety-critical applications. However, since battery technology no longer advances commensurately with integration density, multi-core platforms may have limited utility in battery-powered embedded systems. In this paper, we propose an energy-budget-aware reliability management (enBudRM) method for multi-core embedded systems featuring hybrid energy source (with renewable and non-renewable energy sources). Our method is composed of two phases. In the offline phase, we only consider battery as the energy source and, according to the available energy-budget and slack time for each execution frame, tasks scheduling and voltage-frequency level are determined such that the tasks timing constraints are met while achieving the given reliability target. To increase the battery lifetime, in the online phase, we exploit released slack time at runtime for further voltage scaling. To compensate for the reliability loss of voltage scaling, we exploit an energy harvester along with the battery to enable executing more task replicas. Our experiments show that our energy budgeting method (the offline phase) compared to other approaches reduces the energy consumption on average by 57% (up to 80%). Also, by using harvester we can achieve up to 45% (on average 35%) battery energy saving, resulting in a higher battery life.

Topology-dependent behavior of wireless communication makes the modeling and verification of Mobile Ad hoc Networks (MANETs) more complicated. Reliable Restricted Broadcast Process Theory (RRBPT) was introduced to specify and analyze MANETs in an algebraic approach. Constrained Action Computation Tree Logic (CACLT), interpreted over the semantics of RRBPT, allows to specify topology-dependent properties of MANETs. However, model checking of CACTL formulae is restricted to MANETs with a small number of nodes or finite datatypes. Having an algebraic specification, the problem of model checking of CACTL properties can be reduced to solving Boolean equations, as an intermediate formalism. This technique has been followed in the mCRL2 toolset to verify -calculus properties extended with data. Having a sound translation from RRBPT to mCRL2, we can use its toolset to verify data-dependent properties of MANET processes with infinite state, data-dependent behaviors. By treating the topology-dependent behavior of CACTL modals as data, we can also verify topology-dependent behavior of MANETs. To this aim, we provide a sound translation from CACTL formulae to first order modal -calculus expressions. Our translation takes advantage of the formal treatment of data and parametrized propositional variables in the mCRL2 process and property specifications respectively to address the topology-formulae part of CACTL expressing multi-hop constrains over the topology.