In this paper, a fractional-N frequency synthesizer based on type-III phase locked loop (PLL) architecture is proposed for frequency modulated continuous wave (FMCW) radar systems. Analysis of the type-III PLL shows that it generates linear frequency ramps more accurately compared with its type-II counterpart and its steady-state phase error is zero, independent of the loop bandwidth and rate of the frequency variation. Considering the stability issues, power consumption, output phase noise and accuracy of the frequency ramp generation, design procedure of the type-III FMCW frequency synthesizer is presented in this paper. Based on this procedure, a fractional-N frequency synthesizer, which generates the triangular frequency sweep by a delta-sigma modulator, is designed at the center frequency of 10 GHz with frequency variation rate of 2 MHz/µ s. Simulation results of the circuit, designed in a 0. 18µ m CMOS technology, illustrates that the frequency error is reduced by about 34% compared to the type-II PLL, designed at the same power consumption.