A Digital Design and Hardware Architecture for the HPRF Radar Signal Processor

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Firouzi m.j.; DALILI OSKOUEI H.; FATEMI MOFRAD R.

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Paper Information

Journal: JOURNAL OF ADVANCED SIGNAL PROCESSING Year:2019 | Volume:3 | Issue:1 (3) Page(s): 77-81

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Title

A Digital Design and Hardware Architecture for the HPRF Radar Signal Processor

Author(s)

Firouzi m.j. | DALILI OSKOUEI H. | FATEMI MOFRAD R. | Issue Writer Certificate

Keywords

High-pulse repetition frequency radar

clutter

FPGA chip

pulse-doppler processing

XSG system generator software

Abstract

Today, the design and use of high-frequency repeater radars are very common because of the advantages of high power transmission and coping with extended clutters and jamming [1]. However, it is always the design and implementation of digital processors that can handle system parameters such as the wide dynamic range above the input signal of these radar coverage has been challenging. In this paper, a method for digital design and determination of the hardware architecture of a high repetition frequency radar signal processor based on the use of software provided by Xilinx XSG It's easier to design and develop The FPGA-based chip-based is provided in the MATLAB Simulink software is presented, this method is based on the use of Software provided by Xilinx Inc. The results of hardware simulation and comparison of output blocks of processing blocks with the output of the analog blocks of the typical radar and comparison with analog digital combined hardware of general radars represent improvement dynamic range of input at least 70 dB and low weight of this processor for a radar with high pulse repetition frequency.

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APA: Copy

Firouzi, m.j., DALILI OSKOUEI, H., & FATEMI MOFRAD, R.. (2019). A Digital Design and Hardware Architecture for the HPRF Radar Signal Processor. JOURNAL OF ADVANCED SIGNAL PROCESSING, 3(1 (3) ), 77-81. SID. https://sid.ir/paper/268944/en

Vancouver: Copy

Firouzi m.j., DALILI OSKOUEI H., FATEMI MOFRAD R.. A Digital Design and Hardware Architecture for the HPRF Radar Signal Processor. JOURNAL OF ADVANCED SIGNAL PROCESSING[Internet]. 2019;3(1 (3) ):77-81. Available from: https://sid.ir/paper/268944/en

IEEE: Copy

m.j. Firouzi, H. DALILI OSKOUEI, and R. FATEMI MOFRAD, “A Digital Design and Hardware Architecture for the HPRF Radar Signal Processor,” JOURNAL OF ADVANCED SIGNAL PROCESSING, vol. 3, no. 1 (3) , pp. 77–81, 2019, [Online]. Available: https://sid.ir/paper/268944/en

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