A LOW-JITTER 20-110 MHZ DLL BASED ON A SIMPLE PD AND COMMON-MODE VOLTAGE LEVEL CORRECTED DIFFERENTIAL DELAY ELEMENTS

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KAZEMINIA SARANG; HADIDI KHAYROLLAH; KHOEI ABDOLLAH

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Paper Information

Journal: Journal of Information Systems and Telecommunication Year:2014 | Volume:2 | Issue:3 (7) Page(s): 166-172

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Title

A LOW-JITTER 20-110 MHZ DLL BASED ON A SIMPLE PD AND COMMON-MODE VOLTAGE LEVEL CORRECTED DIFFERENTIAL DELAY ELEMENTS

Author(s)

KAZEMINIA SARANG | HADIDI KHAYROLLAH | KHOEI ABDOLLAH | Issue Writer Certificate

Keywords

DELAY LOCKED LOOP

CLOCK GENERATION

LOW-JITTER CLOCK DISTRIBUTION

WIDE-RANGE DLL

LOW-JITTER DLL

Abstract

In this paper, a 16-phases 20 MHz to 110MHz low jitter DELAY LOCKED LOOP, DLL, is proposed in a 0.35 mm CMOS process. A sensitive open loop phase detector, PD, is introduced based on a novel idea to simply detect small phase differences between reference clock and generated delayed signals. High sensitivity, besides the simplicity reduces the dead zone of PD and gives a better jitter on output generated clock signals, consequently. A new strategy of common mode setting is utilized on differential delay elements which no longer introduce extra parasitics on output nodes and brings the duty cycle of generated clock signals near to 50 percent. Also, small amplitude differential clock is carefully transferred inside the circuit to considerably suppress the noise effect of supply voltage. Post-Layout simulation results confirm the RMS jitter of less than 6.7 ps at 20 MHz and 2 ps at 100 MHz input clock frequency when the 3.3 Volts supply voltage is subject to 75 mVolts peak-to-peak noise disturbances. Total power consumption reaches from 7.5 mW to 16.5mW when the operating frequency increases from 20MHz to 100MHz. The proposed LOW-JITTER DLL can be implemented in small active area, around 380 mm × 210 mm including the CLOCK GENERATION circuit, which is proper to be repeatedly used inside the chip.

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APA: Copy

KAZEMINIA, SARANG, HADIDI, KHAYROLLAH, & KHOEI, ABDOLLAH. (2014). A LOW-JITTER 20-110 MHZ DLL BASED ON A SIMPLE PD AND COMMON-MODE VOLTAGE LEVEL CORRECTED DIFFERENTIAL DELAY ELEMENTS. JOURNAL OF INFORMATION SYSTEMS AND TELECOMMUNICATION (JIST), 2(3 (7)), 166-172. SID. https://sid.ir/paper/332644/en

Vancouver: Copy

KAZEMINIA SARANG, HADIDI KHAYROLLAH, KHOEI ABDOLLAH. A LOW-JITTER 20-110 MHZ DLL BASED ON A SIMPLE PD AND COMMON-MODE VOLTAGE LEVEL CORRECTED DIFFERENTIAL DELAY ELEMENTS. JOURNAL OF INFORMATION SYSTEMS AND TELECOMMUNICATION (JIST)[Internet]. 2014;2(3 (7)):166-172. Available from: https://sid.ir/paper/332644/en

IEEE: Copy

SARANG KAZEMINIA, KHAYROLLAH HADIDI, and ABDOLLAH KHOEI, “A LOW-JITTER 20-110 MHZ DLL BASED ON A SIMPLE PD AND COMMON-MODE VOLTAGE LEVEL CORRECTED DIFFERENTIAL DELAY ELEMENTS,” JOURNAL OF INFORMATION SYSTEMS AND TELECOMMUNICATION (JIST), vol. 2, no. 3 (7), pp. 166–172, 2014, [Online]. Available: https://sid.ir/paper/332644/en

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