Designing Systolic Array for SL0 Algorithm Implementation

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NASERI A.; Jozpiri R.

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Paper Information

Journal: JOURNAL OF ELECTRONIC AND CYBER DEFENCE Year:2020 | Volume:7 | Issue:4 Page(s): 59-65

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Title

Designing Systolic Array for SL0 Algorithm Implementation

Author(s)

NASERI A. | Jozpiri R. | Issue Writer Certificate

Keywords

Systolic arrayQ1

Parallel processingQ2

SL0 algorithmQ1

Matrix multiplicationQ3

Abstract

Systolic architecture is one of most important Parallel processing architectures. In the Systolic array, ALU units are arranged as an array. This array acts synchronously and executes the recursive equations in parallel by applying the proper input. In this paper, the Systolic array for the SL0 is designed and simulated. Simulation results showed that the implementation of this algorithm with a single processor, assuming 4 clocks for executing each recursive equation, requires 4N ^ 3 + 9. 7N ^ 2 + 3. 2N + 18 clocks, while doing it with a Systolic array requires 48n + 32 clocks due to parallel computing and pipelines.

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APA: Copy

NASERI, A., & Jozpiri, R.. (2020). Designing Systolic Array for SL0 Algorithm Implementation. JOURNAL OF ELECTRONIC AND CYBER DEFENCE, 7(4 ), 59-65. SID. https://sid.ir/paper/360523/en

Vancouver: Copy

NASERI A., Jozpiri R.. Designing Systolic Array for SL0 Algorithm Implementation. JOURNAL OF ELECTRONIC AND CYBER DEFENCE[Internet]. 2020;7(4 ):59-65. Available from: https://sid.ir/paper/360523/en

IEEE: Copy

A. NASERI, and R. Jozpiri, “Designing Systolic Array for SL0 Algorithm Implementation,” JOURNAL OF ELECTRONIC AND CYBER DEFENCE, vol. 7, no. 4 , pp. 59–65, 2020, [Online]. Available: https://sid.ir/paper/360523/en

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