Nonvolatile and Low-Power Spintronic Full-Adder for Realization of Process in Memory

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Amirany A.; JAFARI K.; RAJAEI R.

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Journal: NASHRIYYAH -I MUHANDISI -I BARQ VA MUHANDISI -I KAMPYUTAR -I IRAN, A- MUHANDISI -I BARQ Year:2020 | Volume:18 | Issue:2 Page(s): 111-116

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Title

Nonvolatile and Low-Power Spintronic Full-Adder for Realization of Process in Memory

Author(s)

Amirany A. | JAFARI K. | RAJAEI R. | Issue Writer Certificate

Keywords

Magnetic tunnel junctionQ1

low-power designQ1

spintronicQ1

process in memoryQ1

mybrid MTJ/CMOS circuitsQ1

Abstract

As technology nodes shrink below 90 nm, high static power consumption has become one of the biggest problems of CMOS based circuits due to the exponential leakage current of transistors. spintronic devices such as Magnetic tunnel junction (MTJ) due to their fascinating features such as low static power consumption, non-volatility, high endurance, compatibility with CMOS transistors and high-density fabrication are one of the promising candidate for designing hybrid MTJ/CMOS circuits and overcoming high static power consumption of CMOS based circuits. In this paper, a fully nonvolatile and low power hybrid MTJ/CMOS full-adder circuit for Realization of process in memory is proposed. The simulation results show that all the proposed circuit is at least 50% faster than all previous counterparts, the power output delay is 39% lower than the previous design, and does not impose high hardware overhead.

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APA: Copy

Amirany, A., JAFARI, K., & RAJAEI, R.. (2020). Nonvolatile and Low-Power Spintronic Full-Adder for Realization of Process in Memory. NASHRIYYAH -I MUHANDISI -I BARQ VA MUHANDISI -I KAMPYUTAR -I IRAN, A- MUHANDISI -I BARQ, 18(2 ), 111-116. SID. https://sid.ir/paper/395587/en

Vancouver: Copy

Amirany A., JAFARI K., RAJAEI R.. Nonvolatile and Low-Power Spintronic Full-Adder for Realization of Process in Memory. NASHRIYYAH -I MUHANDISI -I BARQ VA MUHANDISI -I KAMPYUTAR -I IRAN, A- MUHANDISI -I BARQ[Internet]. 2020;18(2 ):111-116. Available from: https://sid.ir/paper/395587/en

IEEE: Copy

A. Amirany, K. JAFARI, and R. RAJAEI, “Nonvolatile and Low-Power Spintronic Full-Adder for Realization of Process in Memory,” NASHRIYYAH -I MUHANDISI -I BARQ VA MUHANDISI -I KAMPYUTAR -I IRAN, A- MUHANDISI -I BARQ, vol. 18, no. 2 , pp. 111–116, 2020, [Online]. Available: https://sid.ir/paper/395587/en

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