A SAR ADC with Improved Algorithm for Reduction of Capacitive DAC Elements

Q: How can I download an article?

To download an article from SID, first log in to the site, search for the article title, and click on the 'Download Article' option.

Q: How can I download an ISI article?

To download an ISI article on SID, enter the keyword or article title in the search bar, view the relevant results, click on the desired article, and select the 'Download Article' option.

Q: How can I access the SID database?

To access the SID database, visit SID.ir, create an account, and log in to access scientific resources.

Q: Is downloading articles from SID free?

Some articles on SID are available for free, while others require payment. Details are specified on the article's page.

Takjoo Milad; Reyhani Shahbaz

Scientific Information Database (SID) - Trusted Source for Research and Academic Resources

Journal Paper

Paper Information

Journal: ELECTRONIC INDUSTRIES Year:2021 | Volume:12 | Issue:2 Page(s): 61-69

Download Full-Text

مرکز اطلاعات علمی Scientific Information Database (SID) - Trusted Source for Research and Academic Resources

Persian Verion

View:

492

Download:

Cites:

Information Journal Paper

Title

A SAR ADC with Improved Algorithm for Reduction of Capacitive DAC Elements

Author(s)

Takjoo Milad | Reyhani Shahbaz | Issue Writer Certificate

Keywords

Analog to digital converter

Digital to analog converter

Successive approximation algorithm

Reduced capacitive array

Abstract

This paper presents an 8-bit analog-to-digital converter (ADC) designed using an improved successive approximation Register(SAR). The proposed structure of the SAR converter uses an integrator embedded with a digital-to-analog converter (DAC). The presence of an integrator at the input of the ADC eliminates the need for a sample and hold circuit and is used to generate different voltage levels in the DAC. Thus, the Successive approximation algorithm in the proposed structure has been modified to provide the required voltage levels with a few number of capacitors in the DAC. Therefore, the complexity of the circuit is reduced and less silicon is occupied due to a Reduced capacitive array in DAC. The proposed ADC completes the analog input to digital code conversion in 10 clock pulses. In order to study the proposed method, the SAR ADC is designed and simulated at the transistor level in 0. 18 μ m CMOS technology at 1. 8 V supply voltage. The simulation results show that the ratio of signal to noise and distortion (SNDR) for input bandwidth of 640 kHz is 48. 3 dB, effective number of bit (ENOB) and power consumption are 48. 3 dB, 7. 74 bits and 0. 85 mW, respectively.

Cites

No record.

References

No record.

Cite

APA: Copy

Takjoo, Milad, & Reyhani, Shahbaz. (2021). A SAR ADC with Improved Algorithm for Reduction of Capacitive DAC Elements. ELECTRONIC INDUSTRIES, 12(2 ), 61-69. SID. https://sid.ir/paper/957325/en

Vancouver: Copy

Takjoo Milad, Reyhani Shahbaz. A SAR ADC with Improved Algorithm for Reduction of Capacitive DAC Elements. ELECTRONIC INDUSTRIES[Internet]. 2021;12(2 ):61-69. Available from: https://sid.ir/paper/957325/en

IEEE: Copy

Milad Takjoo, and Shahbaz Reyhani, “A SAR ADC with Improved Algorithm for Reduction of Capacitive DAC Elements,” ELECTRONIC INDUSTRIES, vol. 12, no. 2 , pp. 61–69, 2021, [Online]. Available: https://sid.ir/paper/957325/en

Related Journal Papers

No record.

Related Seminar Papers

No record.

Related Plans

No record.

Recommended Workshops