Improving Register File Access Latency Tolerance in GPUs by Value Reproduction

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BARATI R.; Sadrosadati M.; SARBAZI AZAD H.

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Paper Information

Journal: NASHRIYYAH -I MUHANDISI -I BARQ VA MUHANDISI -I KAMPYUTAR -I IRAN, B- MUHANDISI -I KAMPYUTAR Year:2022 | Volume:20 | Issue:1 Page(s): 13-24

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Title

Improving Register File Access Latency Tolerance in GPUs by Value Reproduction

Author(s)

BARATI R. | Sadrosadati M. | SARBAZI AZAD H. | Issue Writer Certificate

Keywords

GPUs

register file

value re-production

execution units

Abstract

Large register files reduce the performance and energy overhead of memory accesses by improving the thread-level parallelism and reducing the number of data movements from the off-chip memory. Recently, the latency-tolerant register file (LTRF) is proposed to enable high-capacity register files with low power and area cost. LTRF is a two-level register file in which the first level is a small fast register cache, and the second level is a large slow main register file. LTRF uses a near-perfect register prefetching mechanism that warp registers are prefetched from the main register file to the register file cache before scheduling the warp and hiding the register prefetching latency by the execution of other active warps. LTRF specifies the working set of the warps by partitioning the control flow graph into several prefetch subgraphs, called register-interval. LTRF imposes some performance overhead due to warp stall during the register prefetching. Reducing the number of register-intervals can greatly mitigate this overhead, and improve the effectiveness of LTRF. A register-interval is a subgraph of the control flow graph (CFG) where it has to be a single-entry subgraph with a limited number of registers. We observe that the second constrain contributes more in reducing the size of register-intervals. Increasing the number of registers inside the register-interval cannot address this problem as it imposes huge performance and power overhead during the register prefetching process. In this paper, we propose a register-interval-aware re-production mechanism at compile-time to increase register-interval size without increasing the number of registers inside it. Our experimental results show that our proposal improves the effectiveness of LTRF by 29%, and LTRF’ s performance by about 18% (about 30% improvement over baseline GPU architecture). Moreover, our proposal reduces GPU energy and power consumption by respectively 38% and 15%, on average.

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APA: Copy

BARATI, R., Sadrosadati, M., & SARBAZI AZAD, H.. (2022). Improving Register File Access Latency Tolerance in GPUs by Value Reproduction. NASHRIYYAH -I MUHANDISI -I BARQ VA MUHANDISI -I KAMPYUTAR -I IRAN, B- MUHANDISI -I KAMPYUTAR, 20(1 ), 13-24. SID. https://sid.ir/paper/960570/en

Vancouver: Copy

BARATI R., Sadrosadati M., SARBAZI AZAD H.. Improving Register File Access Latency Tolerance in GPUs by Value Reproduction. NASHRIYYAH -I MUHANDISI -I BARQ VA MUHANDISI -I KAMPYUTAR -I IRAN, B- MUHANDISI -I KAMPYUTAR[Internet]. 2022;20(1 ):13-24. Available from: https://sid.ir/paper/960570/en

IEEE: Copy

R. BARATI, M. Sadrosadati, and H. SARBAZI AZAD, “Improving Register File Access Latency Tolerance in GPUs by Value Reproduction,” NASHRIYYAH -I MUHANDISI -I BARQ VA MUHANDISI -I KAMPYUTAR -I IRAN, B- MUHANDISI -I KAMPYUTAR, vol. 20, no. 1 , pp. 13–24, 2022, [Online]. Available: https://sid.ir/paper/960570/en

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