Design and Implementation of a High-Speed and Low-Energy Approximate Full Adder Cell with CNFET Technology Applicable in Image Processing

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Danandeh Fatemeh; Safaei Mehrabani Yavar; Faghih Mirzaee Reza

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Journal Paper

Paper Information

Journal: TABRIZ JOURNAL OF ELECTRICAL ENGINEERING Year:2023 | Volume:53 | Issue:1 Page(s): 25-35

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Title

Design and Implementation of a High-Speed and Low-Energy Approximate Full Adder Cell with CNFET Technology Applicable in Image Processing

Author(s)

Danandeh Fatemeh | Safaei Mehrabani Yavar | Faghih Mirzaee Reza | Issue Writer Certificate

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Abstract

Approximate computing has emerged as a new method to overcome the delay, energy consumption and area consumption of digital circuits. In this paper, a new approximate full-adder cell, which is based on the combination of the standard CMOS and pass transistor logic styles, is presented. The critical path in the structure of a ripple adder equals only one transistor; Therefore, the adder circuit has high speed. Carbon nanotube field-effect transistor (CNFET) technology is used to simulate and implement the proposed cell. Comprehensive simulations are carried out using HSPICE tool against different power supply voltages, output loads, and ambient temperatures. Simulation results confirm that the proposed cell is more efficient than its counterparts in terms of delay, power-delay product (PDP) and energy-delay product (EDP). At the application level, using the MATLAB tool, the application of image blending is used to evaluate the efficiency of the proposed cell. Simulation results of image processing confirm that the proposed cell has a reasonable performance and produces output images with suitable quality for human inference.

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