Design of Multiple-Valued Interconnection Networks with Gate all Around Transistor for Smart Computer Networks

Q: How can I download an article?

To download an article from SID, first log in to the site, search for the article title, and click on the 'Download Article' option.

Q: How can I download an ISI article?

To download an ISI article on SID, enter the keyword or article title in the search bar, view the relevant results, click on the desired article, and select the 'Download Article' option.

Q: How can I access the SID database?

To access the SID database, visit SID.ir, create an account, and log in to access scientific resources.

Q: Is downloading articles from SID free?

Some articles on SID are available for free, while others require payment. Details are specified on the article's page.

Ghoreishi Neda; Navi Keivan; Sabbaghi Nadooshan Reza; Esmaeildoust Mohammad

مرکز اطلاعات علمی Scientific Information Database (SID) - Trusted Source for Research and Academic Resources

Journal Paper

Paper Information

Journal: International Journal of Smart Electrical Engineering Year:2023 | Volume:12 | Issue:1 Page(s): 11-21

Download Full-Text

View:

Download:

Cites:

Information Journal Paper

Title

Design of Multiple-Valued Interconnection Networks with Gate all Around Transistor for Smart Computer Networks

Author(s)

Ghoreishi Neda | Navi Keivan | Sabbaghi Nadooshan Reza | Esmaeildoust Mohammad | Issue Writer Certificate

Keywords

: High speed

Smart Computer networks

Junctionless FET

Multiple-Valued Logic

Interconnection Network

Abstract

In junctionless nanowire transistors, drain-channel-source doping is of the same type and level. Therefore, fabricating junctionless transistors is less complicated than inversion mode transistors. However, the reduced ratio of on current to off-state current (ION/IOFF) in junctionless nanowire transistors has made their operation difficult due to the high impurity scattering in the channel. The larger ION / IOFF ratio indicates an increase in transistor switching speed. In this study, the use of gate oxide engineering is proposed to increase of ION / IOFF ratio. The proposed oxide thickness is 1.5nm, which is a buffer layer with K = 5.7 and a thickness of 0.5nm, and the oxide with a high permittivity factor with K = 29 and a thickness of 1nm. The proposed structure is called GAA-JL-FET-with-oxide buffer layer. In GAA-JL-FET-with-oxide buffer layer, the ION / IOFF ratio has been improved by about 106 and 102 times compared to the structure with K = 3.9 and K = 7.5, respectively. Due to the high switching speed, the GAA-JL-FET-with-oxide buffer layer is applied to design the Multiple-Valued Logic (MVL) Interconnection Network in the voltage mode for the first time using the mixed-mode tool in Silvaco software. The results reveal improving subthreshold parameters of the simulated device significantly enhance the average power, max delay and power delay product (PDP) of the proposed Interconnection Networks.

Multimedia

No record.

Cites

No record.

References

No record.

Cite

Related Journal Papers

No record.

Related Seminar Papers

No record.

Related Plans