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Cites:

Information Journal Paper

Title

Proposing a Novel Write Circuit to Reduce Energy and Delay of Writing Operations in STT-MRAM Memories Using the Temperature Method

Pages

  27-34

Keywords

process variation (PV)Q1
write error (WE)Q1

Abstract

 With the advancement of technology and the shrinking dimensions of transistors in CMOS technology, several challenges have arisen. One of the main concerns in using CMOS-based memory is the high power consumption of this type of memory. Therefore, new and non-volatile memories were introduced to address the shortcomings of conventional volatile memory. One of the emerging non-volatile technologies is STT-MRAM memory, an effective and efficient alternative to conventional memory such as SRAMs due to low leakage power, high density, and short access time. The positive features of STT-MRAMs make it possible to use them at different memory hierarchy levels, especially the cache level. However, STT-MRAMs suffer from high write energy. In this paper, we present a new write circuit using the temperature method; in addition to improving the high write energy, write delay is also improved. The proposed circuit lead to 22. 5% and 18. 62% improvement in energy and writing delay, respectively, compared to the existing methods.

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  • Cite

    APA: Copy

    Hajisadeghi, A.M., Zarandi, H.R., & JALILIAN, SH.. (2021). Proposing a Novel Write Circuit to Reduce Energy and Delay of Writing Operations in STT-MRAM Memories Using the Temperature Method. NASHRIYYAH -I MUHANDISI -I BARQ VA MUHANDISI -I KAMPYUTAR -I IRAN, B- MUHANDISI -I KAMPYUTAR, 19(1 ), 27-34. SID. https://sid.ir/paper/394777/en

    Vancouver: Copy

    Hajisadeghi A.M., Zarandi H.R., JALILIAN SH.. Proposing a Novel Write Circuit to Reduce Energy and Delay of Writing Operations in STT-MRAM Memories Using the Temperature Method. NASHRIYYAH -I MUHANDISI -I BARQ VA MUHANDISI -I KAMPYUTAR -I IRAN, B- MUHANDISI -I KAMPYUTAR[Internet]. 2021;19(1 ):27-34. Available from: https://sid.ir/paper/394777/en

    IEEE: Copy

    A.M. Hajisadeghi, H.R. Zarandi, and SH. JALILIAN, “Proposing a Novel Write Circuit to Reduce Energy and Delay of Writing Operations in STT-MRAM Memories Using the Temperature Method,” NASHRIYYAH -I MUHANDISI -I BARQ VA MUHANDISI -I KAMPYUTAR -I IRAN, B- MUHANDISI -I KAMPYUTAR, vol. 19, no. 1 , pp. 27–34, 2021, [Online]. Available: https://sid.ir/paper/394777/en

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