Information Journal Paper
APA:
CopySHIRAZI, B., WANG, M., & PATHAK, G.. (1993). ANALYSIS AND EVALUATION OF HEURISTIC FOR INTERCONNECTION – CONSTRAINED HETEROGENEOUS PROCESSOR ARCHITECTURES. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 4(2), 75-87. SID. https://sid.ir/paper/556300/en
Vancouver:
CopySHIRAZI B., WANG M., PATHAK G.. ANALYSIS AND EVALUATION OF HEURISTIC FOR INTERCONNECTION – CONSTRAINED HETEROGENEOUS PROCESSOR ARCHITECTURES. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS[Internet]. 1993;4(2):75-87. Available from: https://sid.ir/paper/556300/en
IEEE:
CopyB. SHIRAZI, M. WANG, and G. PATHAK, “ANALYSIS AND EVALUATION OF HEURISTIC FOR INTERCONNECTION – CONSTRAINED HETEROGENEOUS PROCESSOR ARCHITECTURES,” IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, vol. 4, no. 2, pp. 75–87, 1993, [Online]. Available: https://sid.ir/paper/556300/en