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Information Journal Paper

Title

A SYSTEMATIC METHOD FOR TESTING OF BUS-BASED COMMUNICATION STRUCTURES OF COMPLEX CHIPS

Pages

  1-11

Abstract

 Bus based COMMUNICATION STRUCTURES play a key role in communicating between components of high density chips such as System-on-Chip (SOC) and Network-on-Chip (NOC). Many STATIC FAULTS such as open circuit, short circuit, stuck-at and combination of them, and also such as CROSSTALK faults might occur in chip's BUS-based COMMUNICATION STRUCTURES during chip manufacture or in the normal operation of them. Former needs dedicated tests and the latter needs at-speed tests. In this paper we have exploited a systematic method to extract test patterns for both of static and CROSSTALK fault types, and proposed a very suitable solution for testing of chips' BUSes through designing an at-speed test pattern generator for each of fault types with low area overhead.

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  • Cite

    APA: Copy

    NOORMANDIPOUR, REZA, & KHADEMZADEH, AHMAD. (2007). A SYSTEMATIC METHOD FOR TESTING OF BUS-BASED COMMUNICATION STRUCTURES OF COMPLEX CHIPS. THE CSI JOURNAL ON COMPUTER SCIENCE AND ENGINEERING, 5(3 (A)), 1-11. SID. https://sid.ir/paper/70698/en

    Vancouver: Copy

    NOORMANDIPOUR REZA, KHADEMZADEH AHMAD. A SYSTEMATIC METHOD FOR TESTING OF BUS-BASED COMMUNICATION STRUCTURES OF COMPLEX CHIPS. THE CSI JOURNAL ON COMPUTER SCIENCE AND ENGINEERING[Internet]. 2007;5(3 (A)):1-11. Available from: https://sid.ir/paper/70698/en

    IEEE: Copy

    REZA NOORMANDIPOUR, and AHMAD KHADEMZADEH, “A SYSTEMATIC METHOD FOR TESTING OF BUS-BASED COMMUNICATION STRUCTURES OF COMPLEX CHIPS,” THE CSI JOURNAL ON COMPUTER SCIENCE AND ENGINEERING, vol. 5, no. 3 (A), pp. 1–11, 2007, [Online]. Available: https://sid.ir/paper/70698/en

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