Ultra Low Energy DSP Processor Design for Many Core Parallel Applications

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Soltani Farani B.; DOROSTI H.; Salehi M.E.; FAKHRAIE S.M.

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Paper Information

Journal: JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING INNOVATIONS Year:2020 | Volume:8 | Issue:1 Page(s): 71-84

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Title

Ultra Low Energy DSP Processor Design for Many Core Parallel Applications

Author(s)

Soltani Farani B. | DOROSTI H. | Salehi M.E. | FAKHRAIE S.M. | Issue Writer Certificate

Keywords

DSP processor

Ultra

low

energy

sub

threshold circuits

Many

core architectures

Abstract

Background and Objectives: Digital signal processors are widely used in energy constrained applications in which battery lifetime is a critical concern. Accordingly, designing Ultra-low-energy processors is a major concern. In this work and in the first step, we propose a sub-threshold DSP processor. Methods: As our baseline architecture, we use a modified version of an existing Ultra-low-power general purpose processor. Afterwards, we make some modifications to add new instructions to the processor instruction set for better adapting to signal processing applications. In the second step, employing sub-threshold cores in Many-core architectures, we use the proposed processor as simple basic cores in a Many-core architecture. Results: In comparison with the baseline architecture, these modifications reduce the program memory size about 42% in average. In addition, data memory accesses are reduced about 60% in average, and more than 90% speed-up is achieved. According to the improvements in total execution time (93%) and power consumption (27%), the total consumed energy is reduced about 95% in average with at most 2. 6% area overhead and without increasing the process variation effects on processor specifications. Conclusion: The results show that for parallel applications, such as FFT in LTE standard, exploiting sub-threshold processors in a Many-core architecture not only can satisfy the required performance, but also reduce the power consumption about 50% or even more.

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APA: Copy

Soltani Farani, B., DOROSTI, H., Salehi, M.E., & FAKHRAIE, S.M.. (2020). Ultra Low Energy DSP Processor Design for Many Core Parallel Applications. JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING INNOVATIONS, 8(1), 71-84. SID. https://sid.ir/paper/742166/en

Vancouver: Copy

Soltani Farani B., DOROSTI H., Salehi M.E., FAKHRAIE S.M.. Ultra Low Energy DSP Processor Design for Many Core Parallel Applications. JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING INNOVATIONS[Internet]. 2020;8(1):71-84. Available from: https://sid.ir/paper/742166/en

IEEE: Copy

B. Soltani Farani, H. DOROSTI, M.E. Salehi, and S.M. FAKHRAIE, “Ultra Low Energy DSP Processor Design for Many Core Parallel Applications,” JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING INNOVATIONS, vol. 8, no. 1, pp. 71–84, 2020, [Online]. Available: https://sid.ir/paper/742166/en

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