This work presents a sub-nanowatt voltage reference (VR) achieving a high-power supply ripple rejection (PSRR). It utilizes a self-current biasing circuit to reduce the voltage dependency of the output voltage (VREF) to the power supply variations. For low-power operation, all transistors operate in the subthreshold region. The design's performance is verified through post-layout and Monte Carlo simulations in a standard 180 nm CMOS process. Results show that the proposed bandgap achieves an output voltage of 0.150 V with a PSRR of -81.5 dB at V­­dd = 1V. Notably, it eliminates the need for an additional startup circuit and consumes only 0.72 nW at T = 27°C with Vdd = 0.5V. The proposed voltage reference exhibits a temperature coefficient (TC) of approximately 18 ppm/°C over a temperature range of -20°C to 130°C while without using a trimming circuit a reasonable (σ VREF /μVREF) = 2.3% is obtained. This design's average line sensitivity (LS) is 0.072%/V (Vdd = 0.5V to 1.8V). However, the PSRR and LS values are temperature-dependent. At the high temperature of 130°C (worst-case), the PSRR and LS degrade to approximately -80.45 dB and 0.084 %/V, respectively.  The output noise at the frequency of 1 KHz is obtained as 167.34 nV/ √ Hz. The proposed VR occupies a small active area of 513.5 μm2.

In this paper design and analysis of bandgap voltage reference with CMOS transistor for elimination of temperature and source voltage effect is presented. In this paper, by applying techniques such as the base current provider circuit to independent the output voltage from the fabrication process, as well as using a large capacitor and self-bias cascade current mirrors with high swing, the power supply rejection ratio, without affecting the spectral density power, improves. In this design self bias cascade current mirror with high swing is used for decreasing the effect of bias voltage on the output voltage. Two base-emitter voltage with series structure is used for compensation of transistors mismatches, also it used circuits for base current compensation for designing of output voltage independent from the production process, and large capacity for removing external interference. Simulation result of designed bandgap voltage reference with ADS achieves output voltage of 1. 236V; PSRR and output power spectral density at frequency of 100HZ obtained-109. 94 dB and 3. 072 nv/√ HZ, respectively. Also, the output voltage temperature coefficient is 28. 3 ppm/℃ at-40 ℃ to 120 ℃ .

With advancement of integrated circuit technology and aggressive scaling into nanometer regime, statistical variability in device electrical characteristics caused by discreteness of charge and fabrication process variations has significantly increased. These variations in turn result in fluctuations in output characteristics of important analog building blocks and in particular, amplifiers. In this paper, with the aid of Monte-Carlo simulations for a transconductance amplifier and using 1000 different compact models of MOSFET transistors in 35nm technology node, statistical variations of important circuit parameters are investigated and analyzed based on their statistical distributions. Moreover, statistical correlations between circuit parameters are extracted. Analysis of statistical variations for circuit parameters and their correlations has a direct impact on reduction of cost and time of a design and thus, is of great amount of significance.

In this paper a novel common mode separation technique for implementing fully differential current buffers is introduced. Using the proposed method two high CMRR (Common Mode Rejection Ratio) and high PSRR (Power Supply Rejection Ratio) fully differential current buffers in BIPOLAR and CMOS technologies are implemented. Simulation results by HSPICE using 0.18 mm TSMC process for CMOS based structures in 1.4 V supply voltage and transistor models NUHFARRY and PUHFARRY for BJT based one in 1.6 V supply voltage show CMRR of 32.9 dB and 33.1 dB for CMOS based and BJT based fully differential current buffers respectively. The proposed fully differential current buffers show PSRR- of 114 dB and 116 dB in CMOS and BIPOLAR technologies respectively while their PSRR+ are 100 dB and 109 dB respectively. The proposed common mode separation technique can also be arranged in partial positive feedback configuration to provide high current gain too. Simulation results of this configuration in CMOS technology, show current gain and CMRR of 20.86 dB and 53.91 dB respectively. The proposed method tends to be a fundamental technique in current mode signal processing capable to be much further improved and utilized. Favorably, corner case simulation results of the proposed structures prove their robustness against technology process.

 In this paper a new structure for the MLF (Multi Loop Feedback) Gm-C group of filters is presented, granting the advantages of both current-mode and fully balanced topologies to the conventional structure of the group. The ability of the structure to perform even more transfer functions (Low pass and Band Pass) than other members of the group is proved. Methods of enabling the proposed structure to perform other popular transfer functions are also presented. The favorite feature of systematical generation of the structure facilitates its arrangement for any order. For practical comparison, a Butterworth 4th–order LP filter with a cut-off frequency of 10MHz is designed in three different structures viz; the proposed one, the single-ended current mode, and fully balanced voltage mode. Simulation results show that the PSRR+,PSRR-,CMRR, Noise, THD, DR, consumed power (P) and Figure of Merit (FOM) of the new structure compared to its voltage mode counterpart are improved at least by factors of 36643, 59841, 4.75, 76, 2, 2.45, 1.17 and 509500, respectively. Compared to single ended current-mode type they are improved by factors of 40, 73, not defined, 1.3, 7.8, 150, 0.68 and 1763000, respectively. Although the above mentioned comparison, due to both the similarity of the used technology and the completeness of the results, is the most equitable one for the most definite conclusion, to further widen the extent of the comparison, the proposed structure is also compared with some other works yet assumed as its closet counterparts. This latter comparison also proves the certain superiorities of the proposed structure such that its FOM is from 8500 to 4512740 times larger than those of others. Closer tracking of the input signal at pass-band and more attenuation at stop-band are also achieved by this structure. These results strongly support the theoretical suggestions. Most favorably the much higher PSRR of the new structure makes it an extremely suitable choice for Mix-Mode (System-On- a Chip, SOC/SOI) applications where power supplies (and analog blocks) suffer severely from digital noise.

A High-gain, fully balanced preamplifier is presented. The proposed structure advantages flipped voltage follower scheme to achieve a compact current conveyor with very low input impedance. The presented current conveyor then is used as a core element to realize a high-gain, gm-enhanced trans-conductance amplifier. The presented amplifier is suitable for application as a preamplifier. The high gain of amplifier makes it very suitable to be configured in a feedback form to deliver a high-precision predefined or programmable amplification gain. The proposed structure draws a very low power of 150nW from a 0.6V supply voltage. The Spectre Post-layout simulations with TSMC 180nm CMOS technology have been performed. The proposed amplifier exhibits an open-loop DC gain of 141.5dB and 3-dB frequency bandwidth of 2.4kHz at 60dB closed-loop configuration. The load capacitance is set to be 5pF. The proposed structure also delivers high CMRR and PSRR values of 148.3dB and 153.7dB, respectively.

In this paper, a new two-stage OTA is proposed which meeting the needs of high gain, low power and low noise, and designed based on the gm/ID technique with bulk driven method. It is noteworthy that due to the limitations of CMOS technology, CNTFET technology used for the circuit designs. Moreover, to improve the linearity of the circuit, triode transistors used in both stages of amplifiers. The simulation results of the proposed OTA are performed under 1V of supply voltage and 1pF of load capacitors in the HSPICE tool. According to the simulation results, the proposed circuit consumes less than 27 μ W of power and offers a high gain of 98 dB. The CMRR and PSRR values of the proposed circuit are 121 dB and 152 dB, respectively. The input referred noise is 0. 92 nV/√ Hz and the slew rate of the proposed circuit is 111 V/μ s, which shown the better figure of merit (FOM) in compression with the previous works.

In this paper, we propose an efficient approach to design optimization of analog circuits that is based on the reinforcement learning method. In this work, Multi-Objective Learning Automata (MOLA) is used to design a two-stage CMOS operational amplifier (op-amp) in 0. 25μ m technology. The aim is optimizing power consumption and area so as to achieve minimum Total Optimality Index (TOI), as a new and comprehensive proposed criterion, and also meet different design specifications such as DC gain, Gain-Band Width product (GBW), Phase Margin (PM), Slew Rate (SR), Common Mode Rejection Ratio (CMRR), Power Supply Rejection Ratio (PSRR), etc. The proposed MOLA contains several automata and each automaton is responsible for searching one dimension. The workability of the proposed approach is evaluated in comparison with the most well-known category of intelligent meta-heuristic Multi-Objective Optimization (MOO) methods such as Particle Swarm Optimization (PSO), Inclined Planes system Optimization (IPO), Gray Wolf Optimization (GWO) and Non-dominated Sorting Genetic Algorithm II (NSGA-II). The performance of the proposed MOLA is demonstrated in finding optimal Pareto fronts with two criteria Overall Non-dominated Vector Generation (ONVG) and Spacing (SP). In simulations, for the desired application, it has been shown through Computer-Aided Design (CAD) tool that MOLA-based solutions produce better results.