ELECTRONIC INDUSTRIES
Year:2021 | Volume:12 | Issue:1|Papers Count:10

In the paper, we compare two types of systems of Electrical Interconnect (EI) as Near Speed of Light (NSOLT) and Optical Interconnect (OI) on chip for important parameters of delay and power consumption in terms of length interconnection in 22nm CMOS node technology and we obtain critical length for the delay & power consumption parameters. By this comparison, it can be seen that the delay in electrical interconnection system by the near speed of light transmission line method can be less than the optical interconnection, but the power consumption in the optical interconnection on chip at lengths greater than the critical length is less than electrical interconnection even at efficiency power. We also present the best suggestion for optical modulator & photodetector for working on-chip by comparison the different parameters of the types of electro-refractive modulators (carrier injection, carrier depletion) and the types of electro-absorptive modulators as well as comparing the parameters of different types of photodetectors.

One of the factors affecting the positioning error in Loran-C receivers is the accuracy of measuring the time of receiving the signals required to calculate the time difference. Generally, the third zero crossing of the Loran-C signal is used as the basis for determining the receiving time of the pulse, the accuracy of which is highly dependent on the signal-to-noise ratio. The linear digital average algorithm helps to increase the signal-to-noise ratio by averaging the pulses of the consecutive pulse coding intervals received by the Loran-C receiver. The linear digital average in a high-speed receiver, despite the reduction of noise power, distorts the average pulse due to the delay of the participant's pulses. In other words, in fast receivers, in addition to the signal-to-noise ratio and the envelope-to-cycle difference, its distortion is also an important factor in accuracy of the third zero crossing detection. This paper seeks to analyze the effects of the motion vector of the receiver on linear digital average efficiency and to determine the threshold of the receiver’ s velocity to measure the third zero crossing of the average pulse with the desired accuracy. By decomposition of the average pulse into two desirable and undesirable parts, it is getting possible to define the average pulse distortion with known characteristics such as envelope-to-cycle difference and the amplitude attenuation coefficient, and the distortion volume is obtained as a function of velocity vector. The proposed analytical framework is simulated to show the impact of the velocity vector.

In this paper, we propose a duplex blind signature for quantum payment. The features of quantum mechanics have inspired the proposed duplex blind signature. The proposed protocol includes three phases of initialization, signature, and verification. Unlike other blind signatures, in the proposed method, in addition to the signatory who does not see the message, the sender also signs it on transmission. Hence, this method does not rely only on the verifier at the verification phase, but the sender's signature also confirms authenticity of the message. Quantum entanglement and key distribution provides the security of the duplex bind signature. Security analyses indicate that any attacker or any legal person will not be able to forge or disavow the signature in the proposed protocol. It is possible to use the quantum duplex blind signature for e-commerce or electronic payment systems because both quantum entanglement and quantum key distribution have been implemented by today's technology.

In this paper, the phase-shifted pulse width modulation (PWM) method is proposed in an asymmetric three-level neutral point diode clamped (NPC) converter for switched reluctance motor (SRM) drive. In order to control this converter, the level-shifted PWM method is used usually. The proposed modulation method is compared with the level-shifted PWM method on the basis of switching frequency and current ripple. The switching frequency is independent of the load in the proposed method, while current ripple in two cases is almost equal. The switching frequency changes in a nonlinear manner by changing the load in the level-shifted PWM method. Therefore, the switches stress will be increased by the load variation. The effectiveness of the proposed method is verified by theoretical, simulation and comparison results.

Recently, the advances in wireless communications increase demand for low phase noise voltage controlled oscillators (VCO) as one of the most important building block of any frequency synthesizers. Voltage controlled oscillator phase noise is depend on the resonator quality factor. Using superconductors in the metamaterial leads to three unique features of very low losses, smaller dimensions of the structure, and increased resonator quality factor. In this paper, by using these properties in the resonator structure, we have been able to reduce the phase noise in superconducting metamaterial at offset frequency of 100 kHz, in the L band frequency with a tuning range of 150 MHz to value of-150 dBc/Hz. The resonator has been discussed in two types of copper and superconducting metamaterial, and the results are compared with each other. It will be shown how phase noise of voltage controlled oscillators can be reduced by using superconducting microwave resonators.

This research aims to optimize a 6-transistor SRAM cell based on combination of Schmitt trigger not gate and force stack methods. Considering previous studies, a 12-transistor circuit; single-ended is proposed with 22nm technology at voltage 0. 5 volt. There is an opportunity to use this circuit as a Force stack in hold state and in reading mode the cell will be single ended, So Schmitt trigger not gate will inter the circuit, prevents the reading error. The purpose of this study is to optimize the parameters including speed, power and static noise margin. Finally, the effects of replacing CNTFET transistors on parameters has been investigated using simulation. Simulations have been performed by Hspice software at 25° C. Simulation results have shown that the suggested circuit based on CNTs, increases HSNM about 214mV due to using force stack method. Also, in reading mode RSNM increases more than 131mV considering the not Schmitt trigger’ s gate. Since Nano-tube transistors were used, leakage power decrease from nW to pw and circuit’ s delay is optimized.

Recently, the approach of outsourcing database and infrastructure transfer in cloud computing has received a lot of attention from organizations and users. Database owners are trusted by service providers and infrastructure providers in terms of maintainability and accessibility, but are concerned about the confidentiality of information. Therefore, they encrypt the database on cloud servers. The main challenge is to search and retrieve the encrypted database. Although existing searchable encryption schemes allow the user to search and retrieve encrypted data with high reliability, most of these solutions cannot verify the search result. Because the cloud server may only perform part of the search to maintain computing capability or save bandwidth, it may not provide the user with complete and accurate search results. Various searchable encryption schemes that verify and confirm the return results are presented. These schemes usually use a separate method in addition to the algorithms required for confidentiality that increase the processing volume. In this paper, we present a clustered fuzzy keyword search scheme validated on the encrypted database that encrypts and verifies its results using the Authenticated Encryption method. In addition to reducing the volume of stored metadata, reducing the computational burden and increasing the speed of fuzzy search, the proposed scheme acknowledges the return results of the cloud server and is also effective in reducing costs. The proposed plan is safe against the threats considered and retrieves the results correctly and efficiently.

In this paper, an image sensor is introduced which can take photos at high-speed. For this purpose, a pixel readout circuit has been introduced. So that with the same power consumption of the conventional source follower circuit, linearity and accuracy are improved 14dB and 16%, respectively. Total input referred noise of the pixel readout circuit in the band width of 1hz-1GHz is 0. 7mv and power consumption without bias circuit is 16. 9µ w. The proposed image sensor is designed based on the column-parallel architecture, and a new structure has been introduced to convert pixel analog signals to digital, which can convert pixels signals to 10 bits digital data in two consecutive phases. This method has led to 16 times increase in sampling rate without significantly increasing power consumption compared to a conventional single-slope ADC. All circuits are designed in TSMC 0. 18µ m CMOS technology and implemented by Cadence software and simulated by the Spectre circuit simulator.

In this paper, Sigle Ended Primary Inductance Converter (SEPIC) is evaluated. at first, the classical SEPIC circuit and few modified SEPIC converters with some snubber cells are examined. These snubber circuits are used to obtain turn-on and turn-off soft switching for all input voltage ranges and output power variation. Using soft switching technique limits the di/dt at the switch turn-on instant and zero-current switching (ZCS) is obtained. It also can limit the dv/dt at the switch turn-on instant. Since it is better to electrically separate the input and output parts of the circuit with a transformer to increase the voltage gain and to isolate the circuit, in the following, an isolated SEPIC converter is studied. In this case, with the presence of the transformer, the voltage stress on the main switch becomes more intense and the need for snubber circuits becomes necessary. For this reason, some snubber cells are introduced and compared with each other. These circuits were analysed and simulated by “ Orcad Capture” software.