THE CSI JOURNAL ON COMPUTER SCIENCE AND ENGINEERING
Year:2006 | Volume:4 | Issue:2-4 (B)|Papers Count:5

An n-node network, with its nodes numbered from - ën/2û to én/2ù - 1, is a chordal ring with chord lengths 1=s0<s1<...<sk-1<n/2 when an arbitrary node j - ën/2û £ j< én/2ù) is connected to each of the 2k nodes j ± t ai mod n (0£ i<k) via an undirected link, where "mod" represents (nearly) symmetric residues in [- ën/2û, én/2ù - 1].We study a class of chordal rings in which the chord length si is a power of an odd "radix" r, that is, si=ri, for r=2a+1 ³ 3. We show that this class of chordal rings, with their nodes indexed by radix-r integers using the symmetric digit set [-a, a], are easy to analyze and offer a number of advantages in tenns of static network parameters and dynamic performance for many application contexts. In particular, these networks allow a very simple optimal (shortest-path) routing algorithm that generates balanced traffic. We then briefly discuss fault tolerance properties of our networks and point out a number of variations and extensions to the basic structure.

Efficient modulo 2n±1 adders are desirable for computer arithmetic units based on residue number systems (RNS) with the popular moduli set {2n-1, 2n, 2n+1}. Regular n-bit ripple-carry adders or their fast equivalents are suitable for modulo 2n addition. But for the other two moduli a correcting increment/decrement step besides the primary n-bit addition is normally required. Several design efforts have tried to reduce the latency of the correcting step to a small delay not depending on the word length n, leading to one-step modular addition schemes. These include the use of alternative encoding of residues (e.g., diminished-1 representation of modulo 2n+1 numbers), customized (vs. generic) adders (e.g., specialized parallel prefix adders), or compound adders. In this paper we investigate alternative modulo 2n+1 addition schemes, focus on generic one-step adder designs, and use the double-lsb representation of modulo 2n+1 numbers. In a generic modular adder, the central abstract n-bit adder may be replaced by any concrete adder architecture meeting the designer's prescribed measures in time, area and power consumption.

The Grid is an emerging technology for enabling resource sharing and coordinated problem solving in dynamic multi-institutional virtual organizations. This paper presents algorithms, methods, and software for a Grid resource manager, responsible for resource brokering and scheduling in Grids. The broker selects computing resources based on actual job requirements and a number of criteria identifying the available resources, with the aim to minimize the turnaround time for the individual application. In pervious work, we proposed Grid-JQA [8] [9]. In this work we propose an aggregation formula for the QoS parameters. The formula is a unit less combination of the parameters together with weighting factors. It is shown that the formula needs to put into a threshold consideration. A discussion on the threshold and its level is also provided. The paper is finalized by the results obtained from simulation and a comparison study.

In this paper, we introduce a novel anonymous routing protocol for mobile ad hoc network (MANETs), named Pseudo CAR. In the proposed scheme, a random identifier is assigned as pseudonym to each link of a path during route discovery. Such pseudonyms are fastened privately in intermediate nodes to create a virtual chain between communicating nodes. This mechanism is called Chain-based Routing. Through hiding nodes’ identifiers inside the chain, Pseudo CAR sender, receiver, and relationship anonymity in addition to untraceability in the network. In comparison to the similar protocols, the main contributions of Pseudo CAR are its simplicity, flexibility and low imposed computational overhead on the network. The operation of the protocol is validated through both analytical results and simulation experiments.

Fault attack techniques are powerful and efficient cryptanalysis methods to find the secret key of cryptographic devices. Thus, several methods have been introduced to offset this type of side channel attack. On the other hand, some techniques were presented to locate and detect faults in the implementations of symmetric and asymmetric encryption/decryption algorithms. To our best knowledge, this paper is the first article which examines the effectiveness of fault tolerance techniques to prevent fault attacks. Also, we introduce a minimum time redundant method of using the inverse modules for Concurrent Error Detection (CED). The usage of Error Correction Codes (ECe) in implementations of Advanced Encryption Standard (AES) is another approach that is proposed in this article. We present the comparison between the usage of the proposed ECCs to make fault tolerant implementation and to resist against fault attacks. Experimental results of one of the proposed ECCs show that almost all possible faults are detected, while some of them are corrected. Thus, it resists against approximately all injected faults to attack on the implementation of AES algorithm.