A CAD tool for design and optimizing latch comparators

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Yaqubi Ehsan; zahiri seyyed hamid

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Journal Paper

Paper Information

Journal: ELECTRONIC INDUSTRIES Year:2017 | Volume:8 | Issue:3 Page(s): 53-66

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Information Journal Paper

Title

A CAD tool for design and optimizing latch comparators

Author(s)

Yaqubi Ehsan | zahiri seyyed hamid | Issue Writer Certificate

Keywords

Latch ComparatorQ1

Computer Aided Design (CAD)Q1

Transistor SizingQ1

Metaheuristic AlgorithmsQ1

Abstract

In this paper, a CAD tool based on the link between Hspice and a heuristic algorithm called Inclined Planes Optimization (IPO) is provided, which its goal is to obtain an optimal design for voltage comparators. This tool uses detailed models of transistors and considers all parasitic elements, to achieve solutions close to reality. The proposed CAD tool minimizes a multi-objective function and provides several 2-dimensional Pareto-fronts. Therefore, the designer understands the correlation between objective functions and selects the optimal design considering the application requirements. To evaluate the final results, 1000-run of Monte Carlo simulation and PVT verification design is performed.

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APA: Copy

Yaqubi, Ehsan, & zahiri, seyyed hamid. (2017). A CAD tool for design and optimizing latch comparators. ELECTRONIC INDUSTRIES, 8(3 ), 53-66. SID. https://sid.ir/paper/229715/en

Vancouver: Copy

Yaqubi Ehsan, zahiri seyyed hamid. A CAD tool for design and optimizing latch comparators. ELECTRONIC INDUSTRIES[Internet]. 2017;8(3 ):53-66. Available from: https://sid.ir/paper/229715/en

IEEE: Copy

Ehsan Yaqubi, and seyyed hamid zahiri, “A CAD tool for design and optimizing latch comparators,” ELECTRONIC INDUSTRIES, vol. 8, no. 3 , pp. 53–66, 2017, [Online]. Available: https://sid.ir/paper/229715/en

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