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Information Journal Paper

Title

FAULT-TOLERANT 3-D NETWORK-ON-CHIP DESIGN USING DYNAMIC LINK SHARING

Author(s)

 SEYYEDAGHAEI REZAEI SEYYED HOSSEIN | MODARRESSI MEHDI | Issue Writer Certificate 

Pages

  1-7

Abstract

 Emerging 3D technology partitions a larger die into smaller parts and then stacks them in a 3D fashion. This technology can lead to a paradigm shift in on-chip communication design providing higher orders of bandwidth and lower latency. However, due to the aggressively scaled transistors in modern technology nodes, the reliability issue has become into a major concern. In this paper,we leverage these ultra-low-latency vertical links to design a FAULT-TOLERANT 3D NoC architecture. In this architecture, permanent and intermittent defects on links and crossbars are bypassed by borrowing the idle bandwidth from vertically adjacent links and crossbars. Evaluation results under synthetic and realistic workloads show that the proposed fault-tolerance mechanism offers higher reliability and lower performance loss, when compared with state-of-the-art FAULT-TOLERANT 3D NoC designs.

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  • Cite

    APA: Copy

    SEYYEDAGHAEI REZAEI, SEYYED HOSSEIN, & MODARRESSI, MEHDI. (2016). FAULT-TOLERANT 3-D NETWORK-ON-CHIP DESIGN USING DYNAMIC LINK SHARING. JOURNAL OF SOFT COMPUTING AND INFORMATION TECHNOLOGY (JSCIT), 6(1 ), 1-7. SID. https://sid.ir/paper/245862/en

    Vancouver: Copy

    SEYYEDAGHAEI REZAEI SEYYED HOSSEIN, MODARRESSI MEHDI. FAULT-TOLERANT 3-D NETWORK-ON-CHIP DESIGN USING DYNAMIC LINK SHARING. JOURNAL OF SOFT COMPUTING AND INFORMATION TECHNOLOGY (JSCIT)[Internet]. 2016;6(1 ):1-7. Available from: https://sid.ir/paper/245862/en

    IEEE: Copy

    SEYYED HOSSEIN SEYYEDAGHAEI REZAEI, and MEHDI MODARRESSI, “FAULT-TOLERANT 3-D NETWORK-ON-CHIP DESIGN USING DYNAMIC LINK SHARING,” JOURNAL OF SOFT COMPUTING AND INFORMATION TECHNOLOGY (JSCIT), vol. 6, no. 1 , pp. 1–7, 2016, [Online]. Available: https://sid.ir/paper/245862/en

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